1. Day 15: October 13, 2010 Performance: Gates
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems
Day 15: October 13, 2010
Performance: Gates
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2. Previously Delay as RC-charging Transistor: Capacitance, Drive Current
As a function of geometry (W/L)
Gate: Topology, Delay
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3. First Order Delay t = R0C0 R0 = Resistance of minimum size NMOS device
C0 = gate capacitance of minimum size NMOS device
Rdrive = R0/Wn Cg = WC0
Technology independent relative delay
t = R0C0
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4. Try again
What is the delay here?
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5. Day 14: Lesson Don’t drive large fanout with a single stage
Must scale up over a number of stages
…but not too many
Exact number will be technology dependent
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6. Today Miller Effect Sizing Large Fanout Data Dependent Delay
Asymmetry of Inputs
Impact of P & N Mobility differences
Large Fanin
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7. Gates
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8. Data Dependent Delay Resistance depends on input values
delay depends on input data
t-delays assuming minsize?
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9. How Size Equalize rise/fall times Rdrive=R0/2
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10. How Size
For equal rise fall
Rdrive=R0/2
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11. Input Load Input capacitance in each case?
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12. Observe
Ratio of Input Load Capacitance to Output Drive Strength: CILoad/Ids
Differs with gate function
Some gates give more drive per capacitive load we pay
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13. Which Implementation is Faster?
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14. Take Away?
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15. Input (A)Symmetry
If one input is known to be later than other, does it matter where it goes?
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16. How Size Equalize rise/fall times Rdrive=R0/2
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17. Increasing Fanin
What happens to input capacitance as fanin (k) increases
Keeping output drive the same
E.g. Rdrive=R0/2
k-input nand gate has input capacitance:
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18. Fanin Gates slow down with fanin Less drive per input capacitance
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19. Which is Fastest? nand32 nand4-inv-nand4-inv-nand2 (nand2-inv)4-nand2
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20. Lesson Large gates are slow / inefficient
High capacitive load / drive strength
Small gates can be inefficient
Need many stages
Staging over moderate size gates minimizes delay
Exact size will be technology dependent
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21. Admin Project 1 Out Townley office hours this week: 2 week assignment
Should have baseline done (today latest)
Should be making list of ideas to make it fast
Last two lectures might be relevant…
Townley office hours this week:
Today (Wed) 1-2pm
Thursday 1-2pm
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22. Ideas First order reason in t=R0C0 units
Gates have different efficiencies
Drive strength per unit input capacitance
Greater N mobility (than P)
favors nand over nor
Large fanin and fanout slow gates
Decompose into stages
…but not too much
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