1. ECE 465: Digital Systems Lecture Notes # 8
Sequential Circuit (Finite-State Machine) Design
SHANTANU DUTT
Department of Electrical and Computer Engineering
University of Illinois, Chicago
Phone: (312) :
URL:

2. Finite State Machines A finite state machine (FSM) is comprised of:
A set V of states that are memorized information about past inputs OR timing positions (required in order to solve a certain problem).
A set E of transitions that are instances of a function Tr(V, X)  V, where X is the set of primary inputs, that “take” a state Si to a state Sj when a certain value(s) of X occurs.
An o/p function f(V, X)  Y (Mealy) or g(V)  Y (Moore), where Y is the set of o/ps
When do we need an FSM (also known as a sequential circuit) to solve a problem?
When we do not need to remember anything about past inputs, we can solve the problem using a combinational circuit
If we need to use some information about past inputs or a timing position to solve a problem, we need to remember these information (store it in memory), and we need an FSM to do so and to apply logic (combinational circuits) along with this memory to solve a problem. States represent memory of relevant features of past inputs.
00,11/1
01/1
10/0
00,10/1
01,11/1
01,1x/0
00/1
Reset
States
Transitions
Inputs, Output

3. Two Different FSM Functions: Computational, Control
X (2 cc’s)
+ (1 cc)
/ (3 cc’s) r1
ldr1
ldr2
ldr3
ldr4
Stage 1
Stage 2
Stage 3 r2 r3 r4 x a b c d
Control
Signals
Datapath: Connection of functional units (adders, multipliers, comparators, etc.), memory and registers to process data
Computational FSM: Recognizes a pattern in the input string (inputted sequentially) X (e.g. does 1101 occur in it or is # of 1’s a multiple of 3?) or performs a computation (e.g., X mod 5) on it.
Control/Action FSM: Output the right control signals (like mux select, register load) at the right times to control a datapath to perform a computation (e.g., processor CU)
(a) Computational FSM
(b) Control/Action FSM
Computation needed: r4 = (a+b)(c+d)/x

4. Finite State Machine (FSM) Design
• Example : Problem Statement
There is a bit-serial I/P line. Design an FSM that outputs a ‘0’
if an even # of 1’s have been received on the I/P line and the
outputs a ‘1’ otherwise.
When do we need an FSM (i.e., seq ckt) to solve a problem rather than a combinational ckt?
Ans: When the problem requires the design to remember something about past inputs in order to solve the problem.
Note: FSMs are different from counters in the sense that they have external I/Ps, and state transitions are dependent on these I/Ps and the current state.
FSM x
O/p y
CLK

5. Digression 1: Setup Times and Hold Time of FFs
Assume, positive edge-triggered D-FF
THold relates to sensitivity period of FF
(when it responds to inputs just after the +ve edge of the clock appears). D
CLK
TSetup relates to propagation delays of
various gates in the FF.
The high point of
the CLK determines the positive edge’s arrival.
Need the D-input to be stable at least TSetup time before the +ve edge of the clock appears
Need the D-input to remain stable at least THold time after the +ve edge of the clock appears

6. Digression 2: Input Sampling
Tlogic
FFs
External I/Ps
External O/Ps m1 m2 n
Comb.
Logic
CLK
Tsetup
• If a +ve edge trigerred synchronous sequential circuit is being designed,
the counting of the # of 1s (i.e., the sampling of the input(s)),
for a general FSM) essentially occurs Tlogic +Tsetup time before every +ve edge.
CLK x
# of 1s
even
(0)
odd
(1)
(2)
(3)
Tlogic + Tsetup
Sampling
instances

7. Even 0/0 Reset Reset Even 1/1 1/0 1 Odd Odd [1] 0/1
Approach to determining states of a computational FSM (including “pattern”-recognition) as opposed to an “action/control” FSM):
First determine the min # of useful information classes about past i/ps required to solve the problem (requires analytical thinking about the problem)
Each info class  a potential state. From this 1st cut at possible states, determine if there are well-defined transitions from each state for all possible i/p values.
If so then these states can be the final states; states w/o well-defined transitions need to be refined into multiple states w/ some transitions between them and others going external (to other states), to achieve well-defined transitions (see FSM word prob. 1).
• In this problem, only 2 classes of information are reqd: whether an even # of 1s have been received so far, or an odd # of 1s have been received so far & there are well-defined transitions between them. Thus these 2 classes become 2 states.
Solution 1: (Mealy)
0/0
Even
Odd
1/1
1/0
0/1
Reset
Output
Input
Transition
Arc
O/P is dependent
on current state and
input in Mealy
Mealy Machine: Output is associated with the state transition, and appears before the state transition is completed (by the next clock pulse).
Even 1
Reset
[0]
Odd
[1]
Output
Input
Output is
dependent only
on current state
Solution 2: (Moore)
Moore Machine: Output is associated
with the state and hence appears
after the state transition takes place.

8. Determining a Reset State:
A reset state is a state the the FSM (seq ckt) should be in when it is just powered on.
In other words, a reset state is a state the FSM should be in, when it has recvd no i/ps
Based on the above definition, decide if any of the states determined so far can be a reset state (i.e., its defn. is consistent w/ not having received any i/p). E.g., in the parity detector problem, the even state qualifies to be the reset state, as in the reset state no i/ps recvd  zero 1’s recvd  even # of 1’s recvd  it can be the even state
If not, then need to have a separate reset state, and have the correct transitions from this state to the other states (depending on the problem solved by the FSM).
Solution 1: (Mealy)
Solution 2: (Moore)
0/0
Reset
Reset
Even
Even
Input
[0]
Output
1/1
1/0
O/P is dependent
on current state and
input in Mealy 1 1
Input
Output
Odd
Odd
[1]
Transition
Arc
Output is
dependent only
on current state
0/1
Mealy Machine: Output is associated
with the state transition, and appears
before the state transition is completed
(by the next clock pulse).
Moore Machine: Output is associated
with the state and hence appears
after the state transition take place.

9. Moore Machine Model Mealy Machine Model
FFs n
CLK
Output
Logic m2
Next State
Comb. m1
External
I/Ps
External Outputs
FFs
External I/Ps
External O/Ps m1 m2 n
Comb.
Logic
CLK
even 
odd
Mealy Machine Model
Moore Machine Model
Time t : Even I/P 1 = propagation delay of logic of Mealy M/C
2 = propagation delay of O/P
logic unit of Moore M/C
t+TFF
Tlogic(NS) + Tsetup
t+1
t+TCLK
t+TCLK+2 t
O/P=1
(Mealy)
1 = TFF + Tlogic(Mealy o/p)
state
= Even
Mealy/Moore
O/P=0
new x=0
state
= Even
Mealy/Moore
O/P=0
new x=1
state
= Odd
Moore O/P=1
2 = TFF + Tlogic(Moore o/p)

10. State Transition Table (Even-Parity Checker)
Encoding: State Variable A, Even State: A = 0 ; Odd State: A = 1.
A x A y y DA TA
Present
State
Input
Next
Moore
O/P
Mealy
D-FF
Excit.
T-FF
Input variables
to comb. logic
Output functions Q FF
N.S. & O/P
Logic
CLK x y2 A DA Or
FFs y1
N.S.
O/P
Q Q+ D
Q Q+ T
DA= Ax ; TA= x
y1 = A for Moore
y2 = Ax for Mealy
Excitation tables for a D-FF and a T-FF
Mealy and Moore Seq. Circuit Models

11. Moore M/C Implementation
DA= Ax ; TA= x
y1 = A for Moore; y2 = Ax for Mealy
Moore M/C Implementation
a) D-FF
b) T-FF x
A y2 A y1
T Q
D Q
x=1
CLK R Q R Q
CLK
Reset
Reset
Moore O/P is synchronized with clock.
Mealy M/C Implementation
b) T-FF
a) D-FF y1 x y1 1
T Q A
D Q
x=1
CLK R Q R Q
CLK
Reset
Reset
Mealy O/P is not synchronized with clock.
Note: Here Moore and Mealy state transition
functions are the same. This will not always be the case.

12. Difference Between Mealy and Moore Machine
Mealy Moore
(1) O/Ps depend on the present O/Ps depend only on the
state and present I/Ps present state
(2) The O/P changes asyn Since the O/Ps change
-chronously with the just after the state changes,
enabling clock edge and the state change is
synchronous with the
enabling clock edge, O/Ps
change synchronously
with this clock edge
(3) A counter is not a Mealy A counter is a Moore
machine machine (o/ps = state bits)
(4) A Mealy machine will have
the same # or fewer states
than a Moore machine
(5) A Moore machine is easier to reason about and thus design as well as debug.But more expensive. There is no free lunch!

13. Transformations Between Mealy and Moore FSMsC
00,10 / 00
11/11 A
01/11
i/ps
o/ps
Mealy  Moore
(extra states needed) D1
[00]
00,10 11 01 D2
[11]
+ state min.
Mealy
Moore B D C
00,10 / 01
11/01 A
01/01
i/ps
o/ps
[01]
00,10 11 01
Mealy  Moore
(no extra states needed)
Mealy
Moore
As can be seen, Mealy  Moore transformation can result in extra states: Mealy states w/ different o/ps in their input transition arcs will need to be replicated in a Moore FSM, w/ the # of replications = # of different o/ps in the input transitions associated w/ the Mealy state
However, a transformation from Moore  Mealy, will not require any extra state: Each Moore state becomes a Mealy state w/ its o/p indication moving from the state to all its input transition arcs. The Mealy m/c states can be reduced via state min. techs. as in Ex.1.

14. Another example: A simple vending machine
Here is how the control is supposed to work. The vending machine delivers
a package of gum after it has received 15 cents in coins. The machine has a single
coin slot that accepts nickels and dimes, one coin at a time. A mechanical sensor
indicates to the control whether a dime or a nickel has been inserted into the coin slot.
The controller’s output causes a single package of gum to be released down a chute
to the customer.
One further specification: We will design our machine so it does not give
change. A customer who pays with two dimes is out 5 cents!
Coin
Sensor
Vending
Machine
FSM
Gum
Release
Mechanism
Open
Reset
CLK
Vending Machine block diagram
States: 0C 5C
10C
15C

15. Moore and Mealy machine state diagrams for the vending machine FSM
— The figure below show the Moore and Mealy machine state transition diagrams.
Reset / 0
)/0
Reset
Reset
)/0
Reset
0 cent
0 cent
[0]
Reset / 0
Reset
N / 0 N
5 cent
D / 0
5 cent
[0] D
D/1 N
N / 0 D
10 cent
[0]
10 cent
N+D
N+D/1
>=15 cent
[1]
>=15 cent
Reset
Reset / 1
Moore machine
Mealy machine
Moore and Mealy machine state diagrams for the vending machine FSM

16. —State transition table for Moore and Mealy M/C (next state col
—State transition table for Moore and Mealy M/C (next state col. also gives D-FF
excitation).
Present State Inputs Next State Moore Output Mealy Output
Q1 Q D N Q1+ Q Open Open
x x x x
Q+ = D
Q Q+ D
Encoded vending machine state transition table. Note: Do not have to design
for the reset input if FFs have a direct reset inputs. Make sure though that reset state is
encoded as all 0’s if possible; otherwise need FFs w/ asynch. reset as well as set inputs

17. Implementation using D-FFs 00 01 11 10
Q1Q0 DN 00 01 11 10
Q1Q0 DN 00 01 11 10
Q1Q0 DN
x x x x
x x x x
x x x x
K-map for Open (Moore)
K-map for D1
K-map for D0 00 01 11 10
Q1Q0 DN
D1 = Q1 + D + Q0·N
OPEN = Q1·Q0
OPEN = Q1·Q0 + D·Q0 + D·Q1 + N·Q1
Moore
x x x x
Mealy
K-map for Open (Mealy)

18. Similarly, a Mealy implementation; only the OPEN function changes. D Q
CLK
Similarly, a Mealy
implementation;
only the OPEN
function changes. R Q N
OPEN
Reset N Q0 D0 Q0
D Q
CLK Q1 R Q N
Reset
Input transition logic cost = 17 (total gate i/ps) Q1 D
Vending machine FSM implementation based on D flip-flops(Moore).

19. Implementation using J-K FFS
J-K Excitation
Q1 Q D N Q1+ Q J1 K J0 K0
x x
x x
x x
x x x x x x
x x 0
x x 1
x x 0
x x
x x
x x
x x 0
x x 0
x x 0
x x x x x x
Q Q+ J K x x
x 1
x 0
Remapped next-state functions for the vending machine example.

20. 00 01 11 10
Q1Q0 DN 00 01 11 10
Q1Q0 DN
x x
x x
x x
x x
x x x x
x x x x
x x
x x
K-map for J1
K-map for K1 00 01 11 10
Q1Q0 DN 00 01 11 10
Q1Q0 DN
x x
x x
x x
x x
x x x x
x x x x
x x
x x
K-map for J0
K-map for K0
K-maps for J-K flip-flop implementation of vending machine.
J1 = D + Q0·N K1 = 0

21. J-K flip-flop implementation for the vending machine example (Moore).Q0 Q1
J Q
CLK D Q K R
OPEN N Q1 D Q0
J Q
CLK Q K R N
Reset
Input transition logic cost = 12 (total gate i/ps), much less than using D-FFs (17) due to the numerous X’s in the excitation function of a J-K that combinational logic synthesis can use to minimize function cost
J-K flip-flop implementation for the vending machine example (Moore).
Similarly, a Mealy implementation; only the OPEN function changes.

22. Basic Steps in the FSM Design Procedure
(1-3 mainly for Computational FSMs)
1. Understand the problem and determine the minimal # of different information classes about past i/ps required to solve it.
2. Convert these information classes into distinct states (which we informally call tentative states), and determine the state transition diagram of the FSM.
3. If the state transitions between states are well-defined (i.e., for each state and i/p value, it is unambiguous what the next state should be), then these are the final states.
Otherwise, states from which transitions are not well defined need to be split into multiple states (called extra states) so that non-well-defined transitions are then translated to well-defined transitions between the “first” of these states and the remaining extra state(s), and also from the extra state(s) to other original states (see, e.g., FSM prob. 1 next)
4. Determine the reset state
5. Perform state minimization
6. (a) Encode states in binary [optional—perform state assignment for logic minimization] (state bits) & obtain state transition table &FF excitation for desired FF type. Or (b) Implement a one-hot style seq. ckt in which each state is represented by a unique FSM
7. Minimize the output and FF excitation input functions (using K-Maps or QM, for example) and implement the FSM using these FFs and logic gates (or MUXes, PLAs, PALs, etc.).

23. FSM Word Problem 1:
• Design a system that outputs a ‘1’ whenever it receives a multiple
of 3 # of 1’s (i.e., 0, 3, 6, 9, etc. # of 1’s) on a serial input line x.
— Relevant information classes needed to solve the problem:
(A) A multiple of 3 # is received.
(B) A non-multiple of 3 # is received.
Questions to consider:
(1) How do we go from (A)(B)
Ans.: If a ‘1’ is received
(2) How do we go from (B)(A)
Ans.: Not clear. Need to split up (B) further into
(B1): 3y+1 # of 1’s received.
(B2): 3y+2 # of 1’s received.
Where y is an integer  0.

24. Note: (A): is 3y+0 = 3y # of 1’s received.
• Now the transitions between the3 classes of information are clear:
(A)  (B1)  (B2)  (A)
1 received
1 received
1 received
• Hence these classes of information can be considered states of
the required as states of the required FSM:
These 3 states can be represented by 3y+I, i = 0,1,2
Output 00
0/1
Reset
Reset
i=0
i=0
[1]
Input
0/0 1
1/0
i=1
1/1 01 1
i=1
[0]
i=2
1/0
i=2
[0] 10 1
0/0
Mealy Machine
Moore Machine

25. • Design a system that outputs a ‘1’ whenever it receives:
FSM Word Problem 2:
• Design a system that outputs a ‘1’ whenever it receives:
(a) A multiple of 3 # of 1’s AND (b) A non-zero even # of 0’s
E.g., ((0,2) , (3,2) , (3,4) , (6,2) ,···)
— Relevant classes of information: Use D&C to figure this out!
- Break problem into relevant classes of # of 1’s & relevant
classes of # of 0’s
- For # of 1’s: 3y+i, i = 0,1,2
[3 classes]
- For # of 0’s: 2z+j, j = 0,1
For j = 0, we need to distinguish between zero (z = 0)
and non-zero (z > 0) # of 0’s
- Thus we have 3 classes:
2z+0, z = 0 ( 0 )
2z+0, z > 0 ( non-zero even )
2z ( odd )
# of 1’s
# of 0’s

26. The relevant # of 1’s can be represented by i = { 0, 1, 2 }
( # of 1’s = 3y+i )
— The relevant # of 0’s can be represented by j= { 00 , 0>0 , 1 }
( # of 0’s = 2z+j ) where the subscript of the 0 indicates whether
z=0 or z>0.
— Since at any point time, a certain # of 1’s and # of 0’s will have
been received, the state of the system will be given by
a combination of relevant # of 1’s and # of 0’s.
— There are 9 combinations:
{ 0, 1, 2, } X { 00, 0>0, 1 } = (0,00), (0,0>0), (0,1), (1,00), (1,0>0),
(1,1), (2,00), (2,0>0), (2,1) 
# of 1’s # of 0’s
Cartesian
Product

27. (0,00)
(0,0>0)
(1,00)
(0,1)
(2,00)
(1,1)
(2,1)
(1,0>0)
(2,0>0)

28. Note: 0>0  2z+j, j = 0 z > 0 (0,00) (0,0>0) (1,00) (0,1)
Reset
(0,00)
0/0
1/0
1/0
(0,0>0)
(1,00)
0/0
1/0
0/0
0/1
1/0
(0,1)
(2,00)
(1,1)
1/0
0/0
0/0
1/0
(2,1)
0/0
(1,0>0)
1/1
0/0
1/0
0/0
(2,0>0)
1/0

29. Parallel or Interacting FSMs
Another option to solve the previous problem is to have 2 independent FSM’s one for detecting the desired # of 1’s and another for the desired # of 0’s (2 subproblems). The o/p of the combined machine is 1 when both FSM’s are in states w/ o/p = 1
For # of 1’s: 3y+i, i = 0,1,2
[3 classes]: FSM1
For # of 0’s: 2z+j, j = 0,1
For j = 0, we need to distinguish between zero (z = 0) & non-zero (z > 0) # of 0’s [3 classes]: FSM2
j=0
z>0
[1]
j=1
[0]
z=0 1
i=2
[0]
i=1
i=0
[1] 1
Reset
Reset
Each pair of states of the 2 FSMs  a state of the composite fsm (previous design)
FSM2
AND x y
o/p1
o/p2
FSM1
Do we save on FFs here?
What about the general case (in which we divide
an FSM w/ m1*m2 states (derived by considering combinations of m1 and m2 info classes for the 2 sub-problems) into 2 FSMs, one w/ m1 and the 2nd w/ m2 states?
Do we save on logic (here and in general)? Will it be faster?
1 state pair; there are 9, and each pair (S1,i, S2,j) represents that state of the entire system (the 1,2 in the state subscript represents the fsm and i, j the state within the fsm).

30. Parallel or Interacting FSMs (contd)
[0]
i=1
i=0
[1] 1
Reset
j=0
z>0
j=1
z=0
FSM2
AND x y
o/p1
o/p2
FSM1
a state pair
Each pair of states of the 2 FSMs  a state of the composite fsm (previous design)
Q: When can a single FSM design be decomposed into >= 2 simpler parallel fsm’s?
Answer:
When the compound o/p condition can be decomposed into multiple smaller independent o/p conditions (as in this example). In such a case, these smaller conditions (equivalently, sub-problems) can each be determined by a simpler fsm. Each of these simpler fsm’s o/ps are used to determine the final o/p via stitch-up logic that corresponds to how the multiple smaller o/p conditions are logically composed (or “connected”) to form the original o/p condition.
Or, in general, if we can use D&C to decompose the problem into smaller sub-problems (which may not all be the same type) and stitch them up, as we saw for the D&C of combinational circuits. E.g., Problem: System needs to o/p a 1 when a multiple of 6 1’s has been seen. Can this be decomposed into smaller problems? What about 9 1’s (seq. FSM’s)?

31. Moore Mealy Reset Reset 1/1 1/0 1 1 0/1
Appendix: Detailed Mealy vs Moore Timing Diagram
Reset
0/0
Reset
State=0
Even
State=0
Even
[0]
1/1
1/0 1 1 x
N.S.
Logic
State=1
Odd
State=1
Odd
[1] Q D- FF
0/1 Q D
Moore
Mealy
S.T. is complete.
CLK
Assume single bit state information stored in a D-FF
State Transition
is occurring
State Transition
is occurring
S.T. is complete.
CLK x D Q
(state)
even
odd
even
even
odd
odd y2
(Mealy O/P) y1
Moore O/P)