1. Instructor: Alexander Stoytchev
CprE 281: Digital Logic
Instructor: Alexander Stoytchev

2. Fast Adders CprE 281: Digital Logic Iowa State University, Ames, IA
Copyright © Alexander Stoytchev

3. Administrative Stuff
HW 5 is due today

4. Administrative Stuff
HW 6 is out
It is due next Monday (Oct 14)

5. Quick Review

6. The problems in which row are easier to calculate?82 61 - ?? 48 26 - ?? 32 11 - ?? 82 64 - ?? 48 29 - ?? 32 13 - ??

7. The problems in which row are easier to calculate?82 61 - 21 48 26 - 22 32 11 - 21
Why? 82 64 - 18 48 29 - 19 32 13 - 19

8. Another Way to Do Subtraction
82 – 64 = –

9. Another Way to Do Subtraction
82 – 64 = –
= (100 – 64) - 100

10. Another Way to Do Subtraction
82 – 64 = –
= (100 – 64) - 100
= ( – 64) - 100

11. Another Way to Do Subtraction
82 – 64 = –
= (100 – 64) - 100
= ( – 64) - 100
= (99 – 64)

12. Another Way to Do Subtraction
82 – 64 = –
= (100 – 64) - 100
= ( – 64) - 100
Does not require borrows
= (99 – 64)

13. 9’s Complement (subtract each digit from 9)99 64 - 35

14. 10’s Complement (subtract each digit from 9 and add 1 to the result)99 64 -
= 36

15. Another Way to Do Subtraction
82 – 64 = (99 – 64)

16. Another Way to Do Subtraction
9’s complement
82 – 64 = (99 – 64)

17. Another Way to Do Subtraction
9’s complement
82 – 64 = (99 – 64) =

18. Another Way to Do Subtraction
9’s complement
82 – 64 = (99 – 64)
10’s complement =

19. Another Way to Do Subtraction
9’s complement
82 – 64 = (99 – 64)
10’s complement = =
// add the first two

20. Another Way to Do Subtraction
9’s complement
82 – 64 = (99 – 64)
10’s complement = =
// add the first two =
// delete the leading 1
= 18

22. Formats for representation of integersb b b n – 1 1
Magnitude
MSB
(a) Unsigned number b b b b n – 1 n – 2 1
Magnitude
Sign
0 denotes +
1 denotes –
MSB
(b) Signed number
[ Figure 3.7 from the textbook ]

23. Negative numbers can be represented in following ways
Sign and magnitude
1’s complement
2’s complement

24. 1’s complement
Let K be the negative equivalent of an n-bit positive number P.
Then, in 1’s complement representation K is obtained by subtracting P from 2n – 1, namely
K = (2n – 1) – P
This means that K can be obtained by inverting all bits of P.

25. Find the 1’s complement of …

26. Example of 1’s complement addition( + 5 ) + ( + 2 ) + ( + 7 )

27. Example of 1’s complement addition( – 5 ) + ( + 2 ) + ( - 3 )
[ Figure 3.8 from the textbook ]

28. Example of 1’s complement addition( + 5 ) + ( – 2 ) + ( + 3 ) 1 1
[ Figure 3.8 from the textbook ]

29. Example of 1’s complement addition( – 5 ) + ( – 2 ) + ( – 7 ) 1 1
[ Figure 3.8 from the textbook ]

30. 2’s complement
Let K be the negative equivalent of an n-bit positive number P.
Then, in 2’s complement representation K is obtained by subtracting P from 2n , namely
K = 2n – P

31. Deriving 2’s complement
For a positive n-bit number P, let K1 and K2 denote its 1’s and 2’s complements, respectively.
K1 = (2n – 1) – P
K2 = 2n – P
Since K2 = K1 + 1, it is evident that in a logic circuit the 2’s complement can computed by inverting all bits of P and then adding 1 to the resulting 1’s-complement number.

32. Find the 2’s complement of …

33. Quick Way to find 2’s complement
Scan the binary number from right to left
Copy all bit that are 0 from right to left
Stop at the first 1
Copy that 1 as well
Invert all remaining bits

34. Interpretation of four-bit signed integers
[ Table 3.2 from the textbook ]

35. Example of 2’s complement addition( + 5 ) + ( + 2 ) + ( + 7 )
[ Figure 3.9 from the textbook ]

36. Example of 2’s complement addition( – 5 ) + ( + 2 ) + ( – 3 )
[ Figure 3.9 from the textbook ]

37. Example of 2’s complement addition( + 5 ) + ( – 2 ) + ( + 3 ) 1
ignore
[ Figure 3.9 from the textbook ]

38. Example of 2’s complement addition( – 5 ) + ( – 2 ) + ( – 7 ) 1
ignore
[ Figure 3.9 from the textbook ]

40. Example of 2’s complement subtraction( + 5 ) – ( + 2 ) – + ( + 3 ) 1
ignore
[ Figure 3.10 from the textbook ]

41. Example of 2’s complement subtraction( – 5 ) – ( + 2 ) – + ( – 7 ) 1
ignore
[ Figure 3.10 from the textbook ]

42. Example of 2’s complement subtraction( + 5 ) – ( – 2 ) – + ( + 7 )
[ Figure 3.10 from the textbook ]

43. Example of 2’s complement subtraction( – 5 ) – ( – 2 ) – + ( – 3 )
[ Figure 3.10 from the textbook ]

44. Graphical interpretation of four-bit 2’s complement numbers
[ Figure 3.11 from the textbook ]

45. Take Home Message
Subtraction can be performed by simply adding the 2’s complement of the second number, regardless of the signs of the two numbers.
Thus, the same adder circuit can be used to perform both addition and subtraction !!!

46. Adder/subtractor unity y y n – 1 1
Add
Sub
control x x x n – 1 1 c n
-bit adder c n s s s n – 1 1
[ Figure 3.12 from the textbook ]

47. XOR Tricks y
control
out

48. XOR as a repeater y

49. XOR as an inverter y 1

50. Addition: when control = 0y y y n – 1 1
Add
Sub
control x x x n – 1 1 c n
-bit adder c n s s s n – 1 1
[ Figure 3.12 from the textbook ]

51. Addition: when control = 0y y y n – 1 1
Add
Sub
control x x x n – 1 1 c n
-bit adder c n s s s n – 1 1
[ Figure 3.12 from the textbook ]

52. Addition: when control = 0y y y n – 1 1
Add
Sub
control x x x n – 1 1
yn-1 … y1 y0 c n
-bit adder c n s s s n – 1 1
[ Figure 3.12 from the textbook ]

53. Subtraction: when control = 1y y y n – 1 1
Add
Sub
control x x x n – 1 1 c n
-bit adder c n s s s n – 1 1
[ Figure 3.12 from the textbook ]

54. Subtraction: when control = 1y y y n – 1 1 1
Add
Sub
control 1 1 1 x x x n – 1 1 c n
-bit adder c n s s s n – 1 1
[ Figure 3.12 from the textbook ]

55. Subtraction: when control = 1y y y n – 1 1 1
Add
Sub
control 1 1 1 x x x n – 1 1
yn-1 … y1 y0 c n
-bit adder c n s s s n – 1 1
[ Figure 3.12 from the textbook ]

56. Subtraction: when control = 1y y y n – 1 1 1
Add
Sub
control 1 1 1 x x x n – 1 1
yn-1 … y1 y0 c n
-bit adder c n 1
carry for the
first column! s s s n – 1 1
[ Figure 3.12 from the textbook ]

57. Examples of determination of overflow( + 7 ) ( – 7 ) + ( + 2 ) + + ( + 2 ) + ( + 9 ) ( – 5 ) c = c = 4 4 c = 1 c = 3 3 ( + 7 ) ( – 7 ) + ( – 2 ) + + ( – 2 ) + ( + 5 ) 1 ( – 9 ) 1 c = 1 c = 1 4 4 c = 1 c = 3 3
[ Figure 3.13 from the textbook ]

58. Examples of determination of overflow( + 7 ) ( – 7 ) + ( + 2 ) + + ( + 2 ) + ( + 9 ) ( – 5 ) c = c = 4 4 c = 1 c = 3 3 ( + 7 ) ( – 7 ) + ( – 2 ) + + ( – 2 ) + ( + 5 ) 1 ( – 9 ) 1 c = 1 c = 1 4 4 c = 1 c = 3 3
[ Figure 3.13 from the textbook ]

59. Examples of determination of overflow( + 7 ) ( – 7 ) + ( + 2 ) + + ( + 2 ) + ( + 9 ) ( – 5 ) c = c = 4 4 c = 1 c = 3 3 ( + 7 ) ( – 7 ) + ( – 2 ) + + ( – 2 ) + ( + 5 ) 1 ( – 9 ) 1 c = 1 c = 1 4 4 c = 1 c = 3 3
[ Figure 3.13 from the textbook ]

60. Calculating overflow for 4-bit numbers
with only three significant bits

61. Calculating overflow for n-bit numbers with only n-1 significant bits

62. Another way to look at the overflow issue

63. Another way to look at the overflow issue
If both numbers that we are adding have the same sign
but the sum does not, then we have an overflow.

64. Can we perform addition even faster?
The goal is to evaluate very fast if the carry from the previous stage will be equal to 0 or 1.

65. Decomposing the Carry calculation

67. Figure 3.14. A ripple-carry adder based on Expression 3.3.g p g p 1 1 c 1 c c 2
Stage 1
Stage 0 s s 1
Figure A ripple-carry adder based on Expression 3.3.

68. Figure 3.15. The first two stages of a carry-lookahead adder.x y x y 1 1 x y g p g p 1 1 c c 2 c 1 s s 1
Figure The first two stages of a carry-lookahead adder.

69. Figure 3.16. A hierarchical carry-lookahead adder with x y x y x y 31 – 24 31 – 24 15 – 8 15 – 8 7 – 7 – c 8 c
Block c
Block
Block c c 32 3 24 16 1 s s s 31 – 24 15 – 8 7 –
Figure A hierarchical carry-lookahead adder with
ripple-carry between blocks.

70. Figure 3.17. A hierarchical carry-lookahead adder.x y x y x y 31 – 24 31 – 24 15 – 8 15 – 8 7 – 7 –
Block
Block
Block c 3 c 1 24 G P G P G P 3 3 1 1 s s s 31 – 24 15 – 8 7 – c c c 32 16 8
Second-level lookahead
Figure A hierarchical carry-lookahead adder.

71. Questions?

72. THE END