1. Design and Use of Memory-Specific Test Structures to Ensure SRAM Yield and Manufacturability F. Duan, R. Castagnetti, R. Venkatraman, O. Kobozeva and S. Ramesh LSI Logic Corporation

2. ISQED-2003 2 Outline n Products need very high-density and high-performance memories without sacrificing yield and manufacturability n LSI Logics Industry-leading 1.87um 2 embedded SRAM bitcell in 130 nm CMOS SoC technology n Need for SRAM-specific test structures to ensure robustness and manufacturability –Accurately shows process-design interaction –Correlate to SRAM yield –Direct feedback for rapid process-improvement –Accurate SRAM device and cell characterization –RAMPCM for design rule robustness validation n Summary

3. ISQED-2003 3 LSI Logic SRAM Technology for SoC n Smallest production high-density SRAM in 180nm and 130nm technology n Fabricated by standard CMOS SoC process High-Density and High-Performance 6T-SRAM for System-on-Chip in 130 nm CMOS Technology, 2001 VLSI Technology Symposium, pp. 105-106, W. Kong, R. Venkatraman, R. Castagnetti, F. Duan and S. Ramesh.

4. ISQED-2003 4 Why Do We Need for SRAM-specific Test Structure? An Example (b)(c) (a) Structures to test metal bridging

5. ISQED-2003 5 Electrical Test Data Only structure (a) detects the early metal /contact bridging

6. ISQED-2003 6 Features of Our Structures n Compared to the conventional structures, our structures: –More product-driven than process-development-driven –Accurately show process-design interaction –Correlate to functionality and yield directly –Identify the yield limiting factors quickly for fast process or design improvements. –Sensitive enough for ongoing monitoring and process transfers.

7. ISQED-2003 7 Test Structure Design and Results n Yield correlation and improvement n SRAM manufacturability n SRAM device and cell characterization n RAMPCM chip –Functional SRAM test chip –Used for SRAM design rule validation

8. ISQED-2003 8 Test Structures of Front-end Critical Layer Monitor n Critical layers: island, poly and contact n Monitor bridging current from intra- and inter- layers n Monitor shared-contact connection

9. ISQED-2003 9 Test Structures of Back-end Monitor n Monitor bridging current from: –Contact and metal 1 (blue arrows) –Metal 2 (red arrows) –Metal 3 (black arrow)

10. ISQED-2003 10 Example of a Test Structure For Poly Bridging Test cell Test array

11. ISQED-2003 11 Poly Bridging Data 100,000 cells No poly bridging found in SRAM

12. ISQED-2003 12 Metal Bridging and Correlation to SRAM Yield 100,000 cells Detected early metal /contact bridging

13. ISQED-2003 13 Metal Bridging and Correlation to SRAM Yield (cont.) Metal bridging identified as yield limiting factor

14. ISQED-2003 14 Metal 1 Bridging Data after Process Improvement 100,000 cells No metal bridging seen after improvement

15. ISQED-2003 15 Test Structures for Manufacturability n An illustration of test structure n List of test structures n Electrical data

16. ISQED-2003 16 An Illustration of the Test Structure n Sizing poly by 5% per side n Build test cell to test its effects on: –Poly to poly bridging –Poly to contact bridging –Pull down transistor leakage

17. ISQED-2003 17 List of Test Structures for SRAM Manufacturability n Sizing island –Island to island bridging –Transistor leakage n Sizing poly –Poly to poly bridging –Poly to contact bridging –Transistor leakage n Sizing contact –Contact to poly bridging –Contact / metal 1 bridging –Contact resistance n Sizing metal 1 –Metal 1 / contact bridging

18. ISQED-2003 18 Effect of Poly Sizing – SRAM Poly to Poly Bridging 100,000 cells Poly to poly spacing in SRAM is robust

19. ISQED-2003 19 Effect of Poly Sizing – SRAM Poly to Contact Bridging 100,000 cells Poly to contact spacing in SRAM is robust

20. ISQED-2003 20 Effect of Poly Sizing – SRAM Pull Down Transistor Leakage 100,000 cells All leakage currents are within device model spec

21. ISQED-2003 21 Test Structures for Characterization n Transistors in SRAM –Due to the environmental difference (OPC, etc), transistors in SRAM may behave differently compared to isolated devices –Need to measure transistor in the real SRAM array for accurate characterization n An illustration of test structures n Electrical data for transistor measurement n Cell characterization

22. ISQED-2003 22 Illustration of Measuring SRAM Transistor

23. ISQED-2003 23 Transistors in SRAM Cell n Measure all the 6 transistors in 6T SRAM –To compare cell symmetry between left and right –To compare with isolated devices n Measure 4 orientations

24. ISQED-2003 24 Saturation Current of Pass Gate Transistors (Left, Right, Isolated Counterpart) Good symmetry and little difference between iso. / dense

25. ISQED-2003 25 Saturation Current of Pull Down Transistors (Left, Right, Isolated Counterpart) Good symmetry and little difference between iso. / dense

26. ISQED-2003 26 Threshold Voltage of Pull Down Transistor in 4 Directions (0, 90, 180, 270) Little difference of 4 different orientations

27. ISQED-2003 27 SNM and Cell Current of 1.87 um 2 Bitcell (130nm Generation) 0.001 0.003 0.005 0.007 0.009 Cell Current (A) Butterfly curve Cell current (L&R)

28. ISQED-2003 28 RAMPCM Test Chip n RAMPCM is a functional SRAM test chip that is used to prove robustness of the most critical SRAM design rules. n Size of the chip is 1M with 1024 row by 1024 columns n Every 64 columns evaluate one critical SRAM design rule

29. ISQED-2003 29 RAMPCM Test Chip (continued) n 8 most critical design rules are evaluated n Each design rule has 4 variations, distributed across array n Data logs from failing dies are used to extract numbers of failing bits per design rule variation

30. ISQED-2003 30 RAMPCM Test Data -- Normalized Failure Rate Design rules used in 1.87 um 2 cell Within process window Note: More than 50Mb data for each variation. This data proves the robustness and manufacturability of the 1.87 um 2 bitcell

31. ISQED-2003 31 Use of Test Structures in 90nm and Beyond n Increased design-process interaction in 90nm and beyond (Ex. OPC variation) n The test structure methodology we have presented today becomes even more necessary for 90 nm and beyond n Gate leakage impact for SRAM must be accurately evaluated n We have designed such necessary test structures for the 90nm node

32. ISQED-2003 32 Summary n We have designed and used SRAM-specific test structures as effective tool for SRAM technology development. n The data from these SRAM test structures provides us direct feedback on process-design interactions and helps to identify yield-limiting factors early and quickly. n The data (including from RAMPCM) is analyzed to prove the robustness and manufacturability of our industry- leading 1.87 um 2 SRAM cell.