1. COMP541 Datapaths I
Montek Singh
Mar 18, 2010

2. Topics Over next 2/3 classes: datapaths Basic register operations
Computer datapaths

3. What is computer architecture?

4. Architecture (ISA) Jumping up a few levels of abstraction.
Architecture: the programmer’s view of the computer
Defined by instructions (operations) and operand locations
Microarchitecture: how to implement an architecture in hardware

5. MIPS Machine Language Three instruction formats:
R-Type: register operands
I-Type: immediate operand
J-Type: for jumps

6. R-Type Register-type 3 register operands: Other fields:
rs, rt: source registers
rd: destination register
Other fields:
op: the operation code or opcode (0 for R-type instructions)
funct: the function
together, the opcode and function tell the computer
what operation to perform
shamt: the shift amount for shift instructions, otherwise it’s 0

7. R-Type Examples Note the order of registers in the assembly code:
add rd, rs, rt

8. I-Type Immediate-type 3 operands: op: the opcode
rs, rt: register operands
imm: 16-bit two’s complement immediate

9. I-Type Examples
Note the differing order of registers in the assembly and machine codes:
addi rt, rs, imm
lw rt, imm(rs)
sw rt, imm(rs)

10. Machine Language: J-Type
Jump-type
26-bit address operand (addr)
Used for jump instructions (j)

11. Review: Instruction Formats

12. Microarchitecture
Microarchitecture: how to implement an architecture in hardware
This is sometimes just called implementation
Processor:
Datapath: functional blocks
Control: control signals

13. Parts of CPUs Datapath Control unit
The registers and logic to perform operations on them
Control unit
Generates signals to control datapath

14. Memory and I/O
Memories are connected to the data/control in and out lines
Example: register to memory ops
Will discuss I/O arrangements later

15. Microoperations Basic operations of the datapath
Example: moving data from one register to another
Not necessarily microprogrammed control
Just a description of operations
You’ll often see architecture described in register transfer lang.

16. Basic Datapath
Copyright © 2007 Elsevier

17. Arithmetic Logic Unit (ALU)
F2:0
Function
000
A & B
001
A | B
010
A + B
011
not used
100
A & ~B
101
A | ~B
110
A - B
111
SLT

18. ALU Design F2:0 Function 000 A & B 001 A | B 010 A + B 011 not used
100
A & ~B
101
A | ~B
110
A - B
111
SLT

19. Set Less Than (SLT) Example
Configure a 32-bit ALU for the set if less than (SLT) operation. Suppose A = 25 and B = 32.
A is less than B, so we expect Y to be the 32-bit representation of 1 (0x ).
For SLT, F2:0 = 111.
F2 = 1 configures the adder unit as a subtracter. So = -7.
The two’s complement representation of -7 has a 1 in the most significant bit, so S31 = 1.
With F1:0 = 11, the final multiplexer selects Y = S31 (zero extended) = 0x

20. Microarchitectures Multiple implementations for a single architecture:
Single-cycle
Each instruction executes in a single cycle
Multicycle
Each instruction is broken up into a series of shorter steps
Pipelined
Each instruction is broken up into a series of steps
Multiple instructions execute at once.

21. Processor Performance
Program execution time
Execution Time =
(# instructions) (cycles/instruction)(seconds/cycle)
Definitions:
Cycles/instruction = CPI
Seconds/cycle = clock period
1/CPI = Instructions/cycle = IPC
Challenge is to satisfy constraints of:
Cost
Power
Performance

22. MIPS Processor
We consider a subset of MIPS instructions (in book & lab):
R-type instructions: and, or, add, sub, slt
Memory instructions: lw, sw
Branch instructions: beq
Later consider adding addi and j

23. Architectural State Following determine state of a processor PC
(32) registers
Memory
Copyright © 2007 Elsevier

24. Next
We’ll look at single cycle MIPS
Then the more complex versions