1. Von Neumann’s First Computer Program
Wing-Kwan Chan
CS 521 – Advanced Computer Architecture
April 3rd, 2008

2. Outline Background History Early EDVAC Next EDVAC Sorting Program
Final EDVAC

3. Background History

4. Background History
ENIAC (Electronic Numerical Integrator and Computer)
Highly parallel computer
Giant computer
Weighing in at over 30 tons 150 feet in length
Over 19,000 vacuum tubes, 1500 relays
Faster than any previous computer
Had only 20 words of internal memory
Requires complicated manual operations for setting up a program on plugboards.
ENIAC could be made at a lower cost.
Known as Electronic Discrete Variable Computer
(EDVAC)
John von Neumann became a consultant to the EDVAC project

5. Early EDVAC

6. Early EDVAC VON Neumann proposed building a serial computer EDVAC
VON Neumann proposed building a serial computer
EDVAC
Electronic Discrete Variable Automatic Computer
The three 32-bit registers
i (for inputs to the arithmetic circuitry, denoted as I)
j (for inputs to the arithmetic circuitry , denoted as J)
o (for output , denoted as A)
bit words of auxiliary memory
divided into 256 "tanks" of 32 words each, operating in a cyclic fashion.
Word 0 of each tank would pass a reading station one bit at a time, then (32 bit-times later) word 1 would be available,..., finally word 31, then word 0 again, etc.
A bit-time was to be 1 µsec, so the cycle time for each tank came 32 x 32 = 1024 µsec.

7. 32-bit words
Serial circuitry found it most convenient to process least significant digit first
Storing Binary in reverse order
Least significant digit on the left
Most significant digit on the right

8. Number Numbers were represented in two’s complement notation1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 b0 b1 b2 b3 b4 b5 b6 b7 b8 b9
b10
b11
b12
b13
b14
b15
b16
b17
b18
b19
b20
b21
b22
b23
b24
b25
b26
b27
b28
b29
b30
b31
0 for numbers
1 for instructions.
sign
Numbers were represented in two’s complement notation
30-bit fractions in the range -1 ≤ x < 1
2-30b b b3 +…+ 2-1b30 – b31
30-bit integer in the range -230 ≤ x < 230 (for Addition, Subtraction and Conversion Operation)
b1 + 2b2 + 4b3+…+ 229b30 – 230b31
Binary coded decimal integer
0000a1a2a3a4b1b2b3b4…g1g2g3g4 (in reverse order)
30-bit fractions in the range -1 ≤ x < 1
2-30b b b3 +…+ 2-1b30 – b31
30-bit fractions in the range -230 ≤ x < 230 (for Addition, Subtraction and Conversion Operation)
b1 + 2b2 + 4b3+…+ 229b30 – 230b31
Binary coded decimal integer
0000a1a2a3a4b1b2b3b4…g1g2g3g4 (in reverse order)

9. Instruction - Operation1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 a0 a1 a2 a3 a4 b0 b1 b2 y0 y1 y2 y3 y4 x0 x1 x2 x3 x4 x5 x6 x7
Operation Code
00000 for Addition
00001 for Subtraction
00010 for Multiplication
00011 for Division
00100 for Square Root
00101 to set A  I
00110 to set A  J
00111 if A>0 then set A  I
if A<0 then set A  J
01000 Set A binary equivalent of decimal number I
01001 Set A  decimal equivalent of binary number of I
**01010, 01011, 01100, 01101, 01110, were reserved for input and output operations which were not specified.

10. Instruction - Variant 111 for holding result in A1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 a0 a1 a2 a3 a4 b0 b1 b2 y0 y1 y2 y3 y4 x0 x1 x2 x3 x4 x5 x6 x7
111 for holding result in A
100 to set J I, I A, A 0
000 for storing result A in memory location yx and set A 0
101 for storing result into the word immediately following this instruction, set A  0 and perform the alter instruction.
110 for storing result into the word immediately following this instruction, set A  0

11. Exceptions 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 a0 a1 a2 a3 a4 b0 b1 b2 y0 y1 y2 y3 y4 x0 x1 x2 x3 x4 x5 x6 x7
Word position
within a tank
Tank Number
Only numbers (not instructions) ever appear in the registers
Only y and x part of that instruction was to be loaded into I, the other bits were clear
If memory location contain an instruction word, only the least significant 13 bits of number in A were to be stored in the yx part

12. Next EDVAC

13. Next EDVAC
New design of EDVAC was never defined in as much detail as the previous one.
It is approximately 80 times faster
improves in machine organization
Introducing “short tanks” with only 1 word each
Provided a small fast-access memory
Increased the number of register and getting rid of register I and J
32 short tanks and 2048 additional words in 64 long tanks.
Not sure: 32 short tanks and 2048 additional words in 64 long tanks.

14. Basic Operation of New EDVAC
C(s) denote the content of short tank number s
PIK s, t, x
Transfer s consecutive words, starting at long tank location x, to s consecutive short tanks, starting at short tank number t. If x is unspecified, the next s words following this instruction are used, and the (s + 1)-th is the next instruction
PUT s, t, x
Transfer s consecutive words, starting at short tank number t, to s consecutive long tank positions starting at location x. If x is unspecified, the next s words following this instruction are used, and the (s + 1)-th is the next instruction.
ADD s, t
Set A  C(s) + C(t).
SUB s, t
Set A  C(s) - C(t).
SEL s, t
If A ≥ 0, set A  C(s); if A < 0, set A  C(t)
TRA x
Go to long tank location x (then x + 1. etc.) for subsequent instructions
JMP s
Go to short tank number s (then s + 1, etc ) for subsequent instructions
STO s
Set C(s)  A.
SET s, t
Set C(s)  C(t)
PIK s, t, x
Transfer s consecutive words, starting at long tank location x, to s consecutive short tanks, starting at short tank number t. If x is unspecified, the next s words following this instruction are used, and the (s + 1)-th is the next instruction
PUT s, t, x
Transfer s consecutive words, starting at short tank number t, to s consecutive long tank positions starting at location x. If x is unspecified, the next s words following this instruction are used, and the (s + 1)-th is the next instruction.

15. Sorting Program

16. Sorting Program
Sorting records into order, and merging two strings of records that have been sorted separately into a single sorted sequence.
Sorting was not described
Only described the merging process

17. Merging Process
n records x0, x1, …, xn-1 are given, consisting of p words each
The first word of each record is called its “key”
key(x0) ≤ key(x1) ≤ … ≤ key(xn-1)
m records y0, y1, …, yn-1 are given
key(y0) ≤ key(y1) ≤ … ≤ key(yn-1)
Merging x’s and y’s together into the merged sequence
key(z0) ≤ key(z1) ≤ … ≤ key(zn+m-1)
Assume that we have found the first l records z0, ,zl+1, where 0 ≤ l ≤ n + m; and assume further that these l records consist of x0, … , xn’-1 and y0, … , ym’-1 in some order, where 0 ≤ n' ≤ n, 0 ≤ m' ≤ m, and n‘ + m’ = l.
There are four cases:
(α) n' < n, m' < m. There are two subcases:
(α1) key(xn’) ≤ key(ym’)
Let z1 = xn’ and replace (l, n', m') by (l + 1, n' + 1, m').
(α2) key(xn’) > key(ym’)
Let z1 = xn’ and replace (l, n', m') by (l + 1, n', m' + 1).
(β) n' < n, m' = m. Same action as (α1).
(γ) n' = n, m' < m. Same action as (α2).
(σ) n' = n, m' = m. The process has been completed.
n=0 1 2 3 4 x0 x1 x2 x3 X4
m=0 1 2 3 4 y0 y1 y2 y3 y4
l=0 1 2 3 4 5 6 7 8 9 z0 z1 z2 z3 z4 z5 z6 z7 z8 z9

18. Von Neumann’s coding in Merging Process
Some interesting coding concepts
Reduce case (β) and (γ) to (α) by giving artificial values 0 and -1 to key(ym’) - key(xn’)
He could made (β) and (γ) equal to (α1) and (α2) to saved four of the short tank location and slightly faster by doing:
“SEL BETA, GAMMA” instead of “SEL, ALPHA1, ALPHA2”
Avoiding the latency problems of delay-line memories & increasing in speed compare to the first EDVAC
A block of p + 1 words is transferred into short tanks, and p words are move into the z area

19. Final EDVAC
The principle of EDVAC’s design were very strong influences on all of the computers constructed during the next decade
The EDVAC project itself continued at the Moore School until August 1949.
The final version of EDVAC
Had a four-address instruction code
Where 4th address specifying the ocation of the next instruction
128 long tanks of memory
each long tanks containing eight 44-bit words
Plus 6 one-word non-addressable short tanks
Auxiliary drum
Basic clock rate of one µsec per bit.
Completed machine processes one word every 48 µsec.