1. UART PC16550 (Universal Asynchronous Receiver/Transmitter) By Derwyn Hollobaugh

2. Example Application of UART
UART (Modem)
Computer
Network
Parallel Data
Serial Data

3. Color Coded Pin Chart of Inputs and Outputs

4. Input and Output Data Lines
D0-D7: Input and Output Data Lines Data can be sent in or out of the chip.
SIN: Serial Input
SOUT: Serial Output

5. Read, Write, Chip Select, and Reset Inputs
WR & WR’ : Write Select (only one of pin needs to be active in order to write)
RD & RD’ : Read Select (only one of pin needs to be active in oder to read)
MR: Master Reset

6. Addresses and Address Strobe
ADS’ : Address Strobe The positive edge of an active ADS’ latches A0-A2 and CS0-CS2’ signals. (This only occurs if the signals are not stable)
CS0, CS1, & CS2’ : Chip Select When CS0 & CS1 are high and CS2’ is low, the chip is selected.
A0, A1, & A2: Address Lines The addresses controls the function of the chip.

7. Baudout, Rclk, Xin, and Xout
Baudout’: Baudout’ is a 16 x clock signal. The clock signal is generated either from the chip or from Xin & Xout.
RCLK: Rclk is a input clock signal from the receiver. Rclk signal must be the same as Baudout’.
Xin: External Crystal Input. This signal input is used generate baud rate oscillator.
Xout: External Crystal Output. This signal output is used to generate baud rate oscillator.

8. RI’, RXRDY’, and TXRDY’
RI’: Ring Indicator indicates that a telephone ringing signal has been received by the modem.
RXRDY’: Receiver DMA signal informs the CPU when there is still data in the Receiver FIFO Register.
TXRDY’: Transmitter DMA signal informs the CPU when the transmitter FIFO register is full.

9. DCD’, DSR’, DTR’, CTS’, and RTS’
DCD’: Data Carrier Detect indicates that the data carrier has been detected by the modem.
DSR’: Data Set Ready indicates the modem is ready to establish the communications link with the UART.
CTS’: Clear to Send indicates that the modem is ready to exchange data.
DTR’: Data Terminal Ready informs modem that the UART is ready to establish a communication link.
RTS’: Request to Send informs the modem that the UART is ready to exchange data.

10. DDIS, OUT1’, OUT2’, and INTR
OUT1’ and OUT2’: These are user- designated output setup by the modem control register.
INTR: Interrupt goes high whenever an error has occurred, received new data, timeout, transmitter register is empty, and modem status.
DDIS: Driver Disable is used when the CPU is accessing data on the UART.

11. Waveform for Read and Write

12. DLAB A2 A1 A0 Register 1 x Receiver Buffer(read),Transmitter Holding
Receiver Buffer(read),Transmitter Holding
Register (write) 1
Interrupt Enable x
Interrupt Identification (read)
FIFO Control (write)
Line Control
MODEM Control
Line Status
MODEM Status
Scratch
Divisor Latch (least significant byte)
Divisor Latch (most significant byte)

13. Handshaking between UART and RS-232
Two Handshakes between UART and RS-232 occur before data is sent
Handshake Number 1
DTR’ goes low and informs modem that the UART is ready to establish communication
DSR’ goes low and indicates modem is ready to establish communication with UART
Handshake Number 2
CTA’’ goes low and informs modem that the UART is ready to exchange data
DSR’ goes low and indicates that the modem is ready to exchange data with the UART

14. After The Two Handshakes
After the two handshakes have occurred, data is exchanged between the UART and modem.
Following the exchange of data, the DCD’ goes low following a change in the modem.
The change in DCD’ causes the INTR to go high. The INTR informs the CPU that there has been a change in data.

15. How the Handshake happens.
DTR’ goes low
DSR’ goes low
DSR’ goes low
DSR’ goes low
Data Exchanged
DCD’ goes low

16. Technical Documents Jameco Technical Document for PC16550DN PC16550DN
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