1. The Verilog Hardware Description Language

2. GUIDELINES
How to write HDL code:

3. GUIDELINES
How NOT to write HDL code:

4. Think Hardware NOT Software
Poorly written HDL code will either be:
Unsynthesizable
Functionally incorrect
Lead to poor performance/area/power results

5. Conventions Verilog IS case sensitive Syntax is based on C
CLOCK, clock and Clock are different
Syntax is based on C
but is interpreted differently

6. Verilog code basic structure
module module_name (ports);
input input_signals;
output output_signals;
inout bidirectional signals;
wire wire_signals;
reg register_type_variables;
primitive/component (ports);
concurrent/sequential assignments
endmodule

7. Port types PORT DIRECTION SIGNAL TYPE - IN -OUT -INOUT
scalar ( input x; )
Vector (input [WIDTH -1 : 0] x)

8. Module port declaration example (1/2)
module and_gate (o, i1, i2);
output o;
input i1;
input i2;
endmodule

9. Module port declaration example (2/2)
module adder (carry, sum, i1, i2);
output carry;
output [3:0] sum;
input [3:0] i1, i2;
endmodule

10. Example

11. Verilog Primitives
Verilog primitives are models of common combinational logic gates
Their functionality is built into the language and can be instantiated in designs directly
The output port of a primitive must be first in the list of ports

12. Structural description example
module gates (o,i0,i1,i2,i3);
output o;
input i0,i1,i2,i3;
wire s1, s2;
and (s1, i0, i1);
and (s2, i2, i3);
and (o, s1, s2);
endmodule

13. Verilog operators Arithmetic Bitwise Relational
+, - , *, Synthesizable
/, % Non-synthesizable
Bitwise
& AND
| OR
~ NOT
^ XOR
~^ XNOR
Relational
=, <, >, <=, >=

14. User-Defined Primitives Truth Table Models
primitive my_UDP (y, x1, x2, x3);
output y; //the output of a primitive cannot be a vector!!
input x1, x2, x3;
table
//x1 x2 x3 : y
0 0 0 : 0;
0 0 1 : 1;
0 1 0 : 0;
0 1 1 : 0;
1 0 0 : 1;
1 0 1 : 0;
1 1 0 : 1;
1 1 1 : 0;
endtable
endprimitive

15. Truth tables with don’t cares
//? Represents a don’t care condition
// on the input
//i1 i2 i3 : y
: 0
: 1
: 0
: 0
1 ? ? : 1
endtable

16. Blocking vs Non-Blocking Assignments
Blocking (=) and non-blocking (<=) assignments appear in sequential (procedural) code only.
Both are not allowed in the same block
The assign statement in non-procedural code is non-blocking

17. Variable Assignment variable_name = value; //blocking assignment
variable_name <= value; //non-blocking assignment
Examples
output a;
output [6:0] b;
reg [3:0] c;
wire [2:0] d;
Correct Incorrect
a = 1; a <= 3;
b <= 7’b ; b = 9’b ;
b[1] = 0;
c <= 0; d <= 0;
d <= {b , c};
b <= {c, d};
b[5:2] <= c;

18. Blocking VS Non-blocking in Simulation
module block();
reg a, b, c; // Blocking assignments
initial begin
a = #10 1'b1;// assign 1 to a at time 10
b = #20 1'b0;// assign 0 to b at time 30
c = #40 1'b1;// assign 1 to c at time 70
end
endmodule
module nonblock(); // Nonblocking assignments
reg a, b, c; // non-blocking assignments initial begin
a <= #10 1'b1;//assign 1 to a at time 10
b <= #20 1'b0;//assign 0 to b at time 20
c <= #40 1'b1;//assign 1 to c at time 40

19. Blocking VS non-blocking in Hardware
Non-blocking assignments are closer to hardware behavior and should be preferred when describing flip-flops and registers.

20. Example
Design an 4-bit shift register. Use first blocking and then non-blocking assignments for the flip-flops. Synthesize your descriptions. Which type of assignment corresponds to correct hardware?

21. Solution
In Verilog, if you want to create sequential logic use a clocked always block with Nonblocking assignments.
If you want to create combinational logic use an always block with Blocking assignments. Try not to mix the two in the same always block.
module shift(Clk,sh1,a);
output [3:0] a;
input Clk,sh1;
reg [3:0]a;
Clk)
begin
a[0] = sh1;
a[1] = a[0];
a[2] = a[1];
a[3] = a[2];
end
endmodule

22. Propagation delay
Used to assign variables or primitives with delay, modeling circuit behaviour
# 5 and (s, i0, i1); ns and gate delay
#5 assign s = i0 & i1; ns and gate delay
#1 assign a = b; --1 ns wire delay
Not synthesizable, is ignored by synthesis tools
Useful in testbenches for creating input signal waveforms
always #20 clk = ~clk ns clock period
#0 rst_n = 0;
#10 rst_n = 1;

23. Concurrent statements –delta time
b = ~ a; (a = 1, b = 1, c =0)
c = a ^ b;
Time a b c δ 2δ

24. Continuous assignment
Multiple driver error
assign c = a & b; ….
assign c = d | e;

25. Combinational circuit description
module gates (d, a, c);
output d;
input a, c;
//reg b;
assign d = c ^ (~a);
// assign b = ~a;
// assign d = c ^ b;
endmodule

26. Arithmetic unit description (full-adder)
module add1 (cout, sum, a, b, cin);
input a, b;
input cin;
output sum;
output cout;
assign {cout,sum} = a + b + cin;
endmodule

27. Example Describe a 5-bit multiplier in Verilog. module Mul(res,a,b);
output [7:0] res;
input [3:0] a,b;
assign res=a*b;
endmodule

28. Conditional assignment - describing MUXs
assign = select_signal ? assignment1 : assignment1
module mux (o, s, i0, i1);
output o;
input i0, i1;
input s;
assign o = s ? i1 : i0;
//if s =1 then o = i1, else o =i0
endmodule

29. Cyclic behavior Statements in cyclic behavior execute sequentially
Can be used to describe either combinational circuits (optional) or sequential circuits (only way)
(sensitivity list)
begin
sequential statements
end

30. Combinational Circuit Description using Cyclic Behavior
(a or b or c)
begin
d = (a & b) | c;
end
ALL input signals must be in sensitivity list or latches will be produced!

31. If statement (sequential)– describing MUXs
if (condition1) begin
signal1 <= value1;
signal2 <= value2;
end
else if (condition2) begin
signal1 <= value3;
signal2 <= value4; …
else
begin
signal1 <= valuen-1;
signal2 <= valuen;
module mux (o, s, i0, i1);
output o;
reg o;
input i0, i1;
input s;
(i0 or i1 or s)
begin
if (s == 0)
o = i0;
else
o = i1;
end
endmodule

32. CASE statement (sequential)– describing MUXs
module mux (o, s, i0, i1);
output o;
reg o;
input i0, i1;
input s;
(i0 or i1 or s)
begin
case (s)
0: o = i0;
1: o = i1;
default: o= 1’bx;
endcase
end
endmodule
case (signal)
value1:
signal1 <= value2;
signal2 <= value3;
value2 :
signal1 <= value4;
signal2 <= value5;
. . .
default:
signal1 <= valuen-1;
signal2 <= valuen;
endcase

33. Example Describe a 3-bit 4-to-1 MUX module mux_4_to_1(o, s, i0, i1);
module mux_3bit_4X1(o, s, i0, i1, i2, i3);
output [2:0] o;
input [2:0] i0, i1, i2, i3;
input [1:0] s;
reg [2:0]o;
(i0 or i1 or i2 or i3 or s)
begin
case (s)
2'b00: o = i0;
2'b01: o = i1;
2'b10: o = i2;
2'b11: o = i3;
endcase
end
endmodule
module mux_4_to_1(o, s, i0, i1);
output [3:0]o;
input [3:0] i0, i1;
input s;
mux u1(o[0], s, i0[0], i1[0] );
mux u2(o[1], s, i0[1], i1[1]);
mux u3(o[2], s, i0[2], i1[2]);
mux u4(o[3], s, i0[3], i1[3]);
endmodule

34. IF VS Case
The case construct, on the other hand, infers a big ol' mux:
The if-else if-else construct infers a priority routing network:

35. CLOCKED PROCESS (Latch with asynchronous reset)
(clk or rst_n)
begin
if (rst_n == 0)
q <= 0;
else if (clk == 1)
q <= d;
end

36. CLOCKED PROCESS (Latch with synchronous reset)
(clk or rst_n)
begin
if (clk == 1)
q <= d;
else if (rst_n == 0)
q <= 0;
end

37. CLOCKED PROCESS (Flip-flop with asynchronous reset)
clk or negedge rst_n)
begin
if (rst_n == 0)
q <= 0;
else
q <= d;
end

38. CLOCKED PROCESS (Flip-flop with synchronous reset)
clk)
begin
if (rst_n == 0)
q <= 0;
else
q <= d;
end

39. for loop statement – shift register
module shift_reg (o, clk, rst_n, i);
output o;
input i;
input clk, rst_n;
reg [3:0] d;
integer k;
(posedge clk or negedge rst_n)
begin
if (rst_n ==0)
d <= 0;
else
d[0] <= i;
for (k=0; k <2; k=k+1)
d[k+1] <= d[k];
end
assign o = d[3];
endmodule

40. CLOCKED VS COMBINATIONAL PROCESS (1/2)
(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
q <= 0;
else
case (c)
0: q = a;
1: q = b;
default: q= 1’bx;
endcase
end
(a or b or c)
begin
case (c)
0: q = a;
1: q = b;
default: q= 1’bx;
endcase
end

41. CLOCKED VS COMBINATIONAL PROCESS (2/2)
(a or b or c)
begin
d = (a & b) | c;
end
(posedge clk)
begin
if (rst_n == 0)
d <= 0;
else
d <= (a & b) | c;
end

42. EXAMPLE
DESCIBE A BINARY UP/DOWN COUNTER WITH ENABLE THAT COUNTS UPTO 12 AND THEN STARTS AGAIN FROM ZERO

43. Task and Function
Read the file document file Task and function

44. Tasks and Functions
A task begins with keyword task and ends with keyword endtask
Inputs and outputs are declared after the keyword task.
Local variables are declared after input and output declaration.
Coding tasks separately allows them to be called from several modules

45. Functions Very similar to tasks Can only have one output
Can call other functions but not tasks
Timing delays are not allowed in functions
A function begins with keyword function and ends with keyword endfunction
inputs are declared after the keyword function.
They can be called with an assignment

46. Task example begin flag=0; for (i=15; i>-1; i=i-1) begin
if (binary[i]== 1 && flag==0) begin
dp=i;
flag=1; end
else
significand[i]=binary[i];
end
exponent= dp;
significand[8:0]=0;
sign=0;
fp={sign,exponent,significand};
endtask
endmodule
module FP_task();
task conv2FP;
input [15:0] binary;
output [31:0] fp;
reg sign;
reg [7:0] exponent;
reg [22:0] significand;
integer i;
integer dp;
integer flag;

47. Calling a Task module FP_task_tb (); FP_task UUT ();
wire [15:0] number;
reg [31:0] fp_out;
assign number=9;
(number)
conv2FP (number, fp_out);
endmodule

48. Common Verilog Pitfalls

49. Name inconsistency Compile: error Severity: Trivial
module wrong_name (o, i0, i1, i2);
output o;
input i1, i2, i3;
assign o = i0 & i1 ^ i2;
endmodule

50. Multiple unconditional concurrent assignments
Simulation: ‘X’ value
Synthesis: ERROR: signal is multiply driven
Severity: Serious
module …
assign x = a & b;
...
assign x = b ^ c;
(b or c)
begin
x <= b | c;
end

51. Incomplete sensitivity list
Simulation: Unexpected behavior
Synthesis: Warning: Incomplete sensitivity list
Severity: Serious
Solution: complete sensitivity list
(a or b)
begin
d <= (a & b) | c; //c is missing from sensitivity list!!!
end

52. Not assigning all outputs in combinational always block
Simulation:
Synthesis: Warning: Signal not always assigned, storage may be needed
Severity: Serious
Solution: assign all signals
(a or b or c)
begin
if (c == 0) then
d <= (a & b) | c; //d assigned only first time,
else if (c == 1)
e <= a; //e assigned only second time!!!
end

53. Unassigned signals Simulation: Undefined value (‘U’)
Synthesis: Warning: Signal is never used/never assigned a value
Severity: Moderate
module …
output y;
input input1, input2;
reg s;
assign y = input1 & input2; //s never assigned
endmodule

54. Output not assigned or not connected
Simulation: Undefined
Synthesis: Error: All logic removed from the design
Severity: Serious
module my_module (o, input1, input2);
output o;
input input1, input2;
reg s;
assign s = input1 & input2; //output never assigned
endmodule

55. Using sequential instead of concurrent process
Simulation: Unexpectedly delayed signals
Synthesis: More FFs than expected

56. TESTBENCH Instructions module types
module testbench();
forever begin
// Inputs
#5 clk=~clk; end
reg clk;
reg rst;
end
reg d;
initial begin
// Outputs
# 20 rst=1;
wire q;
# 30 d=1;
// Instantiate the UUT
# 40 d=0;
# 50 rst=0;
Df d1 (.q(q),.clk(clk),
endmodule
.rst(rst),.d(d));
// Initialize Inputs
initial begin
clk = 0;
rst = 0;
d = 0;
Lect. 3
module Df(q,rst,clk,d);
output q;
reg q;
input clk,rst,d;
or rst)
begin
if (clk == 1)
q <= d;
else if (rst == 0)
end
endmodule

57. TESTBENCH `timescale 1ns / 100ps module testbench_name ();
reg ….; //declaration of register variables for DUT inputs
wire …; //declaration of wires for DUT outputs
DUT_name(DUT ports);
initial $monitor(); //signals to be monitored (optional)
initial begin
#100 $finish; //end simulation
end
initial
begin
clk = 1’b0; //initialize clk
#10 a = 0;
#10 a = 1; …
always # 50 clk = ~clk; //50 ns clk period (if there is a clock)
endmodule

58. TESTBENCH EXAMPLE `timescale 1ns / 100ps module mux_tb ();
reg i0, i1, s;
wire o;
mux M1 (o, s, i0, i1);
initial begin
#100 $finish; //end simulation
end
initial begin //stimulus pattern
#10 i0 = 0; i1=0; s=0;
#10 i0=1;
#10 i0 = 0; i1=1;
#10 i0=0; i1= 0; s=1;
end
endmodule

59. FINITE STATE MACHINES

60. FINITE STATE MACHINE IMPLEMENTATION

61. Mealy Moore machines

62. Verilog Mealy Machine always @(present_state or x)
clr C1 C2
s(t+1)
State Register
next
state
s(t)
present
state
z(t)
x(t)
present
input
or x)
clk
clk or posedge clr)

63. Verilog Moore Machine always @(present_state or x)
clr C2 C1
s(t+1)
z(t)
State Register
next
state
s(t)
present
state
x(t)
present
input
or x)
clk
or x)
clk or posedge clr)

64. FINITE STATE MACHINES
Detect the sequence of 1101

65. Mealy machines (1/5) module fsm (y, clk, rst_n, x); output y;
input clk, rst_n, x;
reg [1:0] state_pr, state_nx;
reg y;
parameter a = 0,
b = 1,
c = 2,
d = 3,
dont_care_state = 2’bx,
dont_care_out = 1’bx;

66. Mealy machines (2/5)
(posedge clk or negedge rst_n) //state memory
begin
if (rst_n == 0)
state_pr <= a; //default state
else
state_pr <= state_nx;
end

67. Mealy machines (3/5) always @ (x or state_pr) //combinational part
begin
CASE (state_pr)
a: if (x == 1) begin
state_nx = b;
y=0;
end
else if (x == 0) begin
state_nx <= a; --optional

68. Mealy machines (4/5) state_nx = c; y=0; --Mealy machine end
b: if (x == 1) begin
state_nx = c;
y=0; --Mealy machine
end
else if (x==0) begin
state_nx <= a;
y=0; --Mealy machine
c: if (x == 1) begin
state_nx = c; --optional
state_nx <= d;

69. Mealy machines (5/5) d: if (x == 1) begin state_nx = b;
y=1; --Mealy machine
end
else if (x==0) begin
state_nx <= a;
y=0; --Mealy machine
default: begin
state_nx = dont_care_state;
y <= dont_care_out;
endcase
endmodule

70. EXAMPLE: OUT-OF-SEQUENCE COUNTER
DESCRIBE A COUNTER WITH THE FOLLOWING SEQUENCE:
“000” => “010” => “011” => “001” => “111” => “000”