1. Parasitic resistance in MOSFETs

2. Series Resistance may limit intrinsic device performance in CMOS scaling
To meet ITRS requirement, the source of high series resistance need to be identified and be minimized.

3. The series resistance can be divided into the four components:
Overlap resistance (Rov);
Extension resistance (Rext);
Deep resistance (Rdp);
Silicide-diffusion contact resistance (Rcsd).

4. Each resistance component consists of the parallel or series combinations of sub-resistance components according to the carrier conduction path and doping profiles and can be modeled as:
with

5. SDE to gate overlap length in the gate length is ~ 30 to 40% as the technology shrinks down (even with “underlap extension” due to dopant diffusion). Key component of Rov is the so-call spreading resistance.

6. Note that the surface potential, yy is not constant over the overlap region!
Vp is the voltage drop in the poly, and Cox is the gate oxide capacitanceand therefore

7. Putting all this together, we have

8. In the case of Rext
Note: Rfr,ext will be more pronounced for the future ultra-short channel device due to possibility of using high-k dielectric sidewall.

9. Derive Similar to Rov we have:

10. In the deep source drain region,

11. where:

12. In the deep source drain region, the contact resistance is actually most critical.

13. Gate dependence of RSD
As VGS increases, parasitic resistance goes down mainly because of the reduction of overlap resistance.

14. Series Resistance Scaling

15. Rcsd and Rov are expected to be dominant components of the total series resistance for future technology.

16. In fact, the sum of Rcsd and Rov’s contributions on total series resistance is about 70 % for 32nm node.

17. PMOSFET
In the case of PMOSFET, due to smaller mobility, RSD is larger, but RSD / Rch is smaller.
Rcsd/Rseries : ~ 60 % , Rov/Rseries : 20 ~ 30 %
for LG < 53 nm

18. To reduce the parasitic resistances, we need advanced source/drain engineering. Particularly, we need to find out how the various device parameters will impact each component of RSD.

19. Increasing SDE doping
~ 50 % reduction in Rext
& ~ 8 % reduction in Rsd
But increasing doping level without controlling of lateral doping slope is not helpful in reducing Rov.
Moreover, N max,ext is closely related to device short channel effect
\ Rov is mainly determined by lateral junction profile slope rather than its maximum doping concentration.

20. Controlling c :
1-decade higher Ndp
 > ~ 60 % reduction in Rcsd & Rsd
Maximizing Ndp (Nif)
 reduce Rsh,dp and 
 Solid-solubility limits problem
(Recall )

21. Alternative barrier height metal of 0. 2 ~ 0
Alternative barrier height metal of 0.2 ~ 0.25 eV ( for example, ErSi2 for NMOS and PtSi2 for PMOS) can be used to reduced Rcsd.

22. Advanced S/D Engineering:
 Box-shaped highly-doped ultrashallow SDE junction
(i.e., laser annealing)
 Schottky Barrier lowering
(i.e., ErSi for NMOS, PtSi2 for PMOS, lower bandgap Si1-xGex layer, etc.)