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DIGITAL ON/OFF AM MODULATOR AMIT R SHARMA & AKRAM SHAZAD.

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Presentation on theme: "DIGITAL ON/OFF AM MODULATOR AMIT R SHARMA & AKRAM SHAZAD."— Presentation transcript:

1 DIGITAL ON/OFF AM MODULATOR AMIT R SHARMA & AKRAM SHAZAD

2 DIGITAL ON/OFF AM MODULATOR
AIM OF THE PROJECT To Design a dedicated hardware module that performs on/off AM MODULATION. The Modulated signal should be 8 bit sinus signal of MHz (carrier freq). The Amplitude of the carrier signal should be configured from microcontroller. The maximum clock freq is 100 MHz.

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What is on on/off AM Modulation. ? Modulation is the process of facilitating the transfer of information over a medium The process of converting information so that it can be successfully sent through a medium is called modulation In amplitude modulation the amplitude of the signal is changed in response to information and all else is kept fixed. (phase and freq)

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REQUIRED WAVEORMS clk i/p o/p No i/p

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OSCILLATOR MODULATOR Bit stream from base band coder of 10ns. The output is a Sine wave With a carrier freq of MHz WISHBONE INTERFACE

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Design of Oscillator The clock freq is of 100 MHz and required freq of the carrier signal should MHz hence we can have a maximum of 8 levels for defining a sine wave. COUNTER clock WAVEOUT Reset Enable SINE LOOKUP TABLE

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/2 2 Amplitude Time (ns)

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Amplitude is controlled By microcontroller using Wishbone interface Low Amplitude Reg High amplitude Reg Idle mode Reg L H oscillator H High amp MUX 1 o/p L Low amp 2 13.56 MHz Low high 3 Idle low 4 s0 s1 00-idle low 01 idle high ”0” ”1” Input data stream 0/1

9 DIGITAL ON/OFF AM MODULATOR Loop- Repeat forOther bit
i/p bit stream IF i/p bit =1 IF No input Check the I/p bit IF i/p bit=0 Sine wave generator Look up table select S0S1=’11’ OUT- A select S0S1=’10 OUT- B select S0S1=’01’ OUT-C select S0S1=’00’ OUT- D Loop- Repeat forOther bit WISHBONE High Ampl Reg Const c1 A MUX SOS1 Low Ampl Reg Const c2 B C Idle Ampl Reg Const c3 D OUT

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RESULTS

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Results from Matlab

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RESULTS FROM VHDL SYNTHESIS REPORT HDL Synthesis Report Macro Statistics # FSMs : 1 # Multipliers : 2 8x8-bit multiplier : 2 # Adders/Subtractors : 2 7-bit adder : 1 1-bit addsub : 1 # Registers : 8 1-bit register : 6 8-bit register : 2 # Multiplexers : 3 1-bit 2-to-1 multiplexer : 1 8-bit 2-to-1 multiplexer : 1 16-bit 2-to-1 multiplexer : 1

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Device utilization summary Selected Device: 3s4000fg900-5 Number of Slices: out of % Number of Slice Flip Flops: out of % Number of 4 input LUTs: out of % Number of bonded IOBs: out of % Number of MULT18X18s: out of % Number of GCLKs: out of % Timing Summary Speed Grade: 5 Minimum period: 2.725ns (Maximum Frequency: MHz) Minimum input arrival time before clock: 3.470ns Maximum output required time after clock: ns Maximum combinational path delay: 7.385ns

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CONCLUSION The design has been successfully implemented by us. The freq of the carrier signal comes out to be MHz. The amplitude of the carrier signal is controllable.

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THANKS FOR ATTENDING OUR PRESENTATION

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