1. Dr. Tassadaq Hussain www.tassadaq.ucerd.com
Introduction to Verilog – Part-3 Expressing Sequential Circuits and FSM

2. Assignment-0 Vendor FPGA Architecture Study:
List/Draw/Table FPGA device portfolio offered by Xilinx and Altera (Intel)
Compare and contrast the FPGA architecture of low-end and high-end devices from both vendors. More specifically, compare the following:
LB Architecture
Logic Cluster Architecture
Block-RAM (BRAM) architecutre
How do Xilinx and Altera architectures differ from each other?
Your report shouldn’t exceed three pages.
Submission deadline: 5th October

3. Review: Sequential Logic
In a combinational circuit, the values of the outputs are determined solely by the present values of its inputs.
A sequential circuit has states, which in conjunction with the present values of inputs determine its behavior. W
Combinational
Combinational
Flip-flops Z
circuit
circuit Q
Clock

4. Review: Sequential Logic
In a sequential circuit, the values of the outputs depend on the past behavior of the circuit, as well as the present values of its inputs.
Moore: If the outputs depend only on the present state.
Mealy: If the outputs depend on both the present state and the present values of the inputs. W
Combinational
Combinational
Flip-flops Z
circuit
circuit Q
Clock

5. Review: Sequential Logic
Sequential circuits can be:
Synchronous – where flip-flops are used to implement the states, and a clock signal is used to control the operation.
Asynchronous – where no clock is used. W
Combinational
Combinational
Flip-flops Z
circuit
circuit Q
Clock

6. Expressing Sequential Logic in Verilog
You have got only one choice:
While combinational circuits can be modeled using continuous assignment or procedural assignment statements.
sequential circuits can be described only with procedural statements.

7. Review: Describing a Positive-Edge D-Flip Flop
CLK is the only input that can cause an event on the output
Therefore CLK is the only signal in the sensitivity list
Special sensitivity Clock):
This event expression tells the Verilog compiler that any reg variable assigned a value in the always construct is the output of a D flip-flop
module flipflop (D, Clock, Q);
input D, Clock;
output reg Q;
Clock)
Q <= D;
endmodule D
CLK Q
D Q

8. Review: Flip-flop Reset Signal
A flip-flop can have either a synchronous or asynchronous reset
Asynchronous Reset: When the reset signal is high, the flip-flop is reset (forced to ‘0’) immediately, regardless of the clock.
Synchronous Reset: On a rising clock edge, if the reset signal is high, The flip-flop is reset (forced to ‘0’).
The difference:
Synchronous reset  flip-flop only resets on a rising clock edge
Asynchronous reset  flip-flop resets immediately

9. D Flip-Flop with (Asynchronous) Reset
module flipflop_ar (D, Clock, Resetn, Q);
input D, Clock, Resetn;
output reg Q;
Clock, negedge Resetn)
if (Resetn == 0)
Q <= 0;
else
Q <= D;
endmodule

10. D Flip-Flop with (Synchronous) Reset
module flipflop_sr (D, Clock, Resetn, Q);
input D, Clock, Resetn;
output reg Q;
Clock)
if (Resetn == 0)
Q <= 0;
else
Q <= D;
endmodule

11. Takeaway So Far …
Expressing Combinational or Sequential circuits using Procedural Statements:
Remember THREE patterns (discussed in the next 3-slides)
Purely based on observation and experience
Not part of IEEE standard (not at all)
Books might not preach that!

12. Three Patterns To Remember - 1
Simulation – outputs are re-evaluated anytime a signal in the sensitivity list changes
Synthesis – The synthesized block’s output may only change when a change occurs on one of the sensitivity list signals
1. Combinational Logic:
Outputs may change when ANY inputs change
Include all input signals in the sensitivity list
always(in1, in2, in3)
in1
Combinational Logic
out
in2
in3

13. Three Patterns To Remember - 2
Simulation – Outputs are re-evaluated anytime a signal in the sensitivity list changes
Synthesis – The synthesized block’s output may only change when a change occurs on one of the sensitivity list signals
2. Sequential Logic with Synchronous Reset:
Outputs may change ONLY when clock changes
Only the clock signal goes in the sensitivity list
always(CLK)
D Q RST D
Reset
CLK Q
Synchronous Reset

14. Three Patterns To Remember -3
Simulation – Outputs are re-evaluated anytime a signal in the sensitivity list changes
Synthesis – The synthesized block’s output may only change when a change occurs on one of the sensitivity list signals
3. Sequential Logic with Asynchronous Reset:
Outputs may change when clock changes or when reset changes
The clock and reset signals go in the sensitivity list
always(CLK, RESET)
D Q RST D
Reset
CLK Q
ASynchronous Reset

15. Review: Flip-flop and Register
A flip-flop stores one bit of information.
When a set of n flip-flops is used to store n bits of information, such as an n-bit number, we refer to these flip-flops as a register.
A common clock is used for each flip-flop in a register, and each flip-flop operates as described in the previously.
The term register is merely a convenience for referring to n-bit structures consisting of flip-flops.

16. Registers module reg4 (D, Clock, Resetn, Q); input [3:0] D;
A 4-bit register with asynchronous clear
module reg4 (D, Clock, Resetn, Q);
input [3:0] D;
input Clock, Resetn;
output reg [3:0] Q;
Clock, negedge Resetn)
if (Resetn == 0)
Q <= 4'b0000;
else
Q <= D;
endmodule

17. Modeling Finite State Machines

18. General Model of a Digital System
DATAPATH – Collection of functional units that process data
Functional units are ultimately implemented as combinational and sequential logic
CONTROLLER – Coordinates the operations in the datapath
(Usually a Finite State Machine)
Controller
System Control Inputs
System Control Outputs
Datapath Control Signals
Datapath Status Signals
System Data Inputs
Datapath
System Data Outputs

19. Review: Moore vs Mealy Which is a Moore FSM and which is Mealy FSM?
State
INPUTS /
Next State Combinational Logic
Output Combinational /
Logic
D Q
D Q /
D Q /
OUTPUTS /
State
INPUTS
Next State Combinational Logic
Output Combinational /
Logic /
D Q /
D Q
D Q /
OUTPUTS /

20. Review: Moore Finite State Machine
Output signals depend only on the current state
Also, observe the THREE distinct parts
State
INPUTS /
Next State Combinational Logic
Output Combinational /
Logic
D Q /
D Q
D Q /
OUTPUTS /
Example State Diagram of a Moore FSM
A = 0 A = 0
A = 0
A = 1 SA
[F = 0] SB
[F = 1]
A = 1 SC
[F = 1] SD
[F = 0]
A = 0
A = 1
A = 1
FSM A F

21. Review: Mealy Finite State Machine
Output signals depend on both current state and current inputs
Also, observe the THREE distinct parts
State
INPUTS
Output Combinational /
Logic /
Next State Combinational Logic
D Q /
D Q
D Q /
OUTPUTS /

22. Moore-type FSM Example
Let’s Work through a Simple
Moore-type FSM Example
3-states FSM
Input = w
Output = z

23. Recipe for Describing FSM in Verilog
Define the state codes as parameters to list all states from your state diagram.
Declare a reg [log2(num states) wide] to store the current state (flip-flops) and next state.
Next-state logic: Write one always block to specify the values that next state should have for each value of present state:
This is a combinational process (Type-1)
Inputs are the current_state (outputs from the first process), and FSM Inputs
Use CASE to specify next state
Outputs are the FSM outputs
Present-state Advancement: Write second always block which specifies that present state is assigned the value of next state on the positive clock edge:
This is a sequential process (Type 2 or 3)
Inputs to this always block are clock and async reset (if any)
Output is the current state signal
Output Logic: Write a third always block (optional) that drives the output based on present state (and input in case of Mealy).
This is a combinational process (Type-1).
Alternatively, can be modeled through continuous statements.

24. 1 2 3 4 5 module moore (Clock, w, Resetn, z); input Clock, w, Resetn;
output z;
parameter A = 2'b00, B = 2'b01, C = 2'b10;
reg [1:0] p_state, n_state;
p_state)
begin
case (p_state)
A: if (w = = 0) n_state = A;
else n_state = B;
B: if (w = = 0) n_state = A;
else n_state = C;
C: if (w = = 0) n_state = A;
default: n_state = 2'bxx;
endcase
end
Clock, negedge Resetn)
if (Resetn = = 0)
p_state <= A;
else
p_state <= n_state;
assign z = (p_state = = C);
endmodule  1 2 3 4 5

25. THANK YOU