1. A Configurable FPGA-Based Traffic Generator for High-Performance Tests of Packet Processing Systems
The Sixth International Conference on Internet Monitoring and Protection (ICIMP 2011)
IPERF: Internet performance      
St. Maarten, The Netherlands Antilles, March 20 – 25, 2011
A. Tockhorn, P. Danielis, D. Timmermann
University of Rostock, Germany
Institute of Applied Microelectronics
and Computer Engineering

2. Outline Introduction & Motivation
Fundamental Functionality of Traffic Generator
Implementation
Summary
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3. Introduction & Motivation
VoIP Emergency Calls
How to get the caller‘s location?
Avoid Phishing: Verification of sender
How to verify the sender‘s identity?
How to localize the phisher?
Support identifying spam
How to provide an additional
trigger for identifying spam?
How to localize the spammer? 3
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4. Introduction & Motivation
IP-Calling Line Identification Presentation
Verifies user provided location information
Adds location information to IP options
Located on linecards in access networks 4
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5. Introduction & Motivation
Increasing bandwidth demands at DeCIX, Frankfurt, GER
Central German peering point
Doubling of bandwidth every year
 Growing requirements for packet processing systems (PPS)
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6. Introduction & Motivation
PPS solely consider header information as decision criteria for packet processing
Processing of small packets is a critical task for PPS
Agilent Technologies: “JTC 003 Mixed Packet Size Throughputs”, White
Paper,
Tips/1MxdPktSzThroughput.pdf, 2001
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7. Introduction & Motivation
Software
Hardware
Combination
Performance - +
Costs O
Configurability
Flexibility
Software
Hardware
Performance - +
Costs
Configurability O
Flexibility
 Combined HW-SW-system
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8. Application Scenario
Main requirements for a configurable traffic generator for the IPclip application scenario:
Configurability of several header options
Configurability of the generated packet sizes
Full utilization of an 1 Gbit/s link
Even for smallest size packet size
Reuse of already existing test cases
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9. Fundamental Functionality
1 Gbit/s
IPClip
Configuration SW
Realize test cases
Configuration of header options
Send configuration sets
Ensure minimal configuration bandwidth
HW Part of TG
Store configuration sets
Build packets to test PPS from configuraton sets
Guarantee desired bandwidth, even full link utilization
Packet processing system under test
Process incoming packets
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10. Fundamental Functionality
Traffic Amplification
Bytes
Set 1
Set 2
Set 3
Frame length (2 bytes) X
IPv4 address (4 bytes)
IPv6 address (16 bytes)
VLAN tag (2 bytes) 2X
LUT index (2 bytes)
Set size in bytes 7 25 9
Config. bandwidth [Mbit/s]
(64 Byte frames) 85
303
109
Amplification 11
3.3
(500 Byte frames) 14 49 18 71 20 55
Bytes
Set 1
Frame length (2 bytes) X
IPv4 address (4 bytes)
IPv6 address (16 bytes)
VLAN tag (2 bytes)
LUT index (2 bytes)
Set size in bytes 7
Config. bandwidth [Mbit/s]
(64 Byte frames) 85
Amplification 11
(500 Byte frames) 14 71
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11. … Implementation Configuration frames
Ethernet frames without standard header
Maximum sized frames
Configuration using regular IP-Packets is also possible
Decrease achievable configuration bandwidth
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12. Implementation Limitations No Jitter measurements
Only statistical traffic patterns possible due to FIFO overruns
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13. Integration into HW Design Flow
Testcase generation ist in C/C++ geschrieben
einfaches Modul, das für die Testbench daraus standardkonforme Pakete generiert
ebenfalls in C/C++ geschriebener Monitor
läuft alles in Simulator (Modelsim, Integration über SystemC)
Testcase generation kann so bleiben, läuft als SW direkt auf PC
Funktion, die daraus mittels winpcap frames an den HW-Traffic Generator schickt
dieser baut frames
monitor durch weiteres fpga und PC ersetzt
auf dem pc können die gleichen Funktionen aus dem Testbench-Monitor laufen
IPClip
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14. Implementation Important issues considered for implementation
Scheduling delays interrupting the configuration software
FIFO running out of configuration sets
Replay already generated frames
Too high demands on the configuration bandwidth
Preconfigure lookup table
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15. High throughput traffic generator:
Summary
High throughput traffic generator:
Affordable traffic generator
Sufficient configurability using configuration software
Instantiating an FPGA plattform enables high throughput
Fulfills all performance requirements
Integrates well into the hardware design process
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16. Thanks for your attention!
Questions?
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