1. ASM and Micro-programmed State Machines
Dr. Tassadaq Hussain
Instructor: Dr. Rehan Ahmed

2. Review: General Model of a Digital System
Digital hardware systems = data-path + control
datapath: registers, counters, combinational functional units (e.g., ALU), communication (e.g., busses)
control: FSM generating sequences of control signals that instructs datapath what to do next
"puppeteer who pulls the strings"
control
status info and inputs
control signal outputs
state
data-path
"puppet"

3. Review FSM: Moore vs Mealy
State
INPUTS /
Next State Combinational Logic
Output Combinational /
Logic
D Q
D Q /
D Q /
OUTPUTS /
State
INPUTS
Next State Combinational Logic
Output Combinational /
Logic /
D Q /
D Q
D Q /
OUTPUTS /

4. Example: FSM as an Arbiter
The purpose of our example arbiter is to control access by various devices to a shared resource in a given system.
Only one device can use the resource at a time.
Assume that all signals in the system can change values only following the positive edge of the clock signal.
Each device provides one input to the FSM, called a request, and the FSM produces a separate output for each device, called a grant.
A device indicates its need to use the resource by asserting its request signal. Whenever the shared resource is not already in use, the FSM considers all requests that are active.
Based on a priority scheme, it selects one of the requesting devices and asserts its grant signal. The devices are assigned a priority level such that device 1 has the highest priority, device 2 has the next highest, and device 3 has the lowest priority.
When the device is finished using the resource, it de-asserts its request signal.

5. Example: FSM as an Arbiter
We will assume that there are three devices in the system, called device 1, device 2, and device 3.
It is easy to see how the FSM can be extended to handle more devices.
The request signals are named r1, r2, and r3, and the grant signals are called g1, g2, and g3.
The devices are assigned a priority level such that device 1 has the highest priority, device 2 has the next highest, and device 3 has the lowest priority. Thus if more than one request signal is asserted when the FSM assigns a grant, the grant is given to the requesting device that has the highest priority.

6. Example: FSM as an Arbiter
Reset 1 2 3
Idle r r 1 1
gnt1 g = 1 1 r r 2 1 r r 1 2
gnt2 g = 1 2 r r 3 2 r r r 1 2 3
gnt3 g = 1 3 r 3

7. Example: FSM as an Arbiter
Reset
000
Idle
0xx
1xx
gnt1 g = 1 1
x0x
1xx
01x
gnt2 g = 1 2
xx0
x1x
001
gnt3 g = 1 3
xx1

8. module arbiter (r, Resetn, Clock, g);
input [1:3] r;
input Resetn, Clock;
output wire [1:3] g;
reg [2:1] y, Y;
parameter Idle = 2'b00, gnt1 = 2'b01, gnt2 = 2'b10, gnt3 = 2'b11;
// Next state combinational circuit y)
case (y)
Idle: casex (r)
3'b000: Y = Idle;
3'b1xx: Y = gnt1;
3'b01x: Y = gnt2;
3'b001: Y = gnt3;
default: Y = Idle;
endcase
gnt1: if (r[1]) Y = gnt1;
else Y = Idle;
gnt2: if (r[2]) Y = gnt2;
gnt3: if (r[3]) Y = gnt3;
// Sequential block
Clock)
if (Resetn == 0) y <= Idle;
else y <= Y;
// Define output
assign g[1] = (y == gnt1);
assign g[2] = (y == gnt2);
assign g[3] = (y == gnt3);
endmodule

9. Algorithmic State Machine (ASM) Charts

10. Algorithmic State Machine (ASM) Charts
Drawbacks of state diagrams for real systems:
Many inputs & many outputs -> awkward to list all of these as each transition arc.
On any given arc
Typically most inputs are don’t care
Typically most outputs are unchanged from the settings in the previous state
Tedious & repetitive to list exhaustively
Not a clear structure for illustrating/designing control flow

11. Algorithmic State Machine (ASM) Charts
An ASM chart is a method of describing the sequential operations of a digital system which has to implement an algorithm.
An algorithm is a well defined sequence of steps that produces a desired sequence of actions and/or calculation results in response to a given sequence of control and data inputs.
ASM charts are similar in appearance to flowcharts used in the early days of computer programming.
Unlike the traditional flowchart the ASM chart includes timing information because it implicitly specifies that the FSM steps from one state to another only after each active clock edge.

12. Key Point to Remember about ASM Charts
A key point to remember about ASM charts is that given a state, they do not enumerate all the possible inputs and outputs. 
Only the inputs that matter and the outputs that are asserted are indicated.

13. Elements used in ASM Charts
State-box
A rectangle represents a state of the FSM. It is equivalent to a node in the state diagram.
The name of the state is indicated outside the box in the top-left corner.
The Moore-type outputs are listed inside the box.
These are the outputs that depend only on the values of the state variables that define the state;
we will refer to them simply as Moore outputs.
Output signals
or actions
(Moore type)
State name

14. Elements used in ASM Charts
Decision Box:
A diamond indicates that the stated condition expression is to be tested and the exit path is to be chosen accordingly.
The condition expression consists of one or more inputs to the FSM.
For example, w indicates that the decision is based on the value of the input w, whereas w1 · w2 indicates that the true path is taken if w1 = w2 = 1 and the false path is taken otherwise.
Condition
expression
0 (False)
1 (True)

15. Elements used in ASM Charts
Conditional Output Box:
An oval denotes the output signals that are of Mealy type.
These outputs depend on the values of the state variables and the inputs of the FSM;
we will refer to these outputs simply as Mealy outputs.
The condition that determines whether such outputs are generated is specified in a decision box
Conditional outputs
or actions (Mealy type)

16. Example: ASM Chart for the Arbiter FSM1 3
Idle
Reset 2
gnt1
gnt2
gnt3 g

17. Class Activity: ASM for Bit Counting Circuit
Suppose that we wish to count the number of bits in a register, A, that have the value 1.
Pseudo-code for a step-by-step procedure, or algorithm,
is shown below:
It assumes that A is stored in a register that can shift its
contents in the left-to-right direction. B = ;
while A  do if a 1
then +
end if;
Right-shift
end while;

18. Class Activity: ASM for Bit Counting Circuit

19. More ASM Examples See chapter 7 - Stephan Brown: 7.3: Bit counting
7.4: Shift and Add Multiplier
7.5: Divider
7.6: Arithmetic Mean
7.7: Sort Operation
Please understand that the above articles are part of our course and therefore questions may be asked in the exam.
Please read and practice through the above articles with due diligence!

20. Micro-programmed State Machines

21. Micro-programmed State Machines
In time shared architecture, computational units are shared to execute different operations of the algorithm in different cycles:
As we have seen in lots of previous examples
In doing that, the controller states are derived from the algorithm/pseudocode.
What if the algorithm or it’s sequencing is updated? OR
Several algorithms need to be implemented on the same datapath
Can we do better than a hardwired FSM?
Make the Controller Programmable

22. Micro-programmed Controller: Idea
In a micro-programmed controller the combinational logic is replaced by a program memory (PM):
PM contains entire sequence of control signals along with the next state.
The address of the PM contents is determined by the current state and input:
Same as we used to compute the next state in a hardwired FSM
Figure from Dr. Shoaib’s Digital Design Book

23. Figure from Dr. Shoaib’s Digital Design Book

24. Counter-based State Machines
Many datapath designs require a simple sequence of control signals from the controller.
Therefore, requiring controller to generate the control words per clock cycle; independent of any input
PM address can come from a counter in that case
Figure from Dr. Shoaib’s Digital Design Book

25. In order to better understand other variations Of Microprogramed SM,
Let’s take a detour and revisit Microprocessor
Pipeline Architecture

26. Review: MIPS Instructions
R-type rs rt rd
shamt
funct
31:26
5:0
25:21
20:16
15:11
10:6
Load/ Store
35 or 43 rs rt
address
31:26
25:21
20:16
15:0 4 rs rt
address
31:26
25:21
20:16
15:0
Branch

27. Datapath Elecments for R-Format Instructions
Read two register operands
Perform arithmetic/logical operation
Write register result

28. Datapath Elements for Load/Store Instructions
Read register operands
Calculate address using 16-bit offset
Use ALU, but sign-extend offset
Load: Read memory and update register
Store: Write register value to memory

29. Branch Instructions Read register operands Compare operands
Use ALU, subtract and check Zero output
Calculate target address
Sign-extend displacement
Shift left 2 places (word displacement)
Add to PC + 4
Already calculated by instruction fetch

30. Datapath Elements for Branch Instructions

31. By the way we need to fetch the instructions as well!

32. Full MIPS Datapath short of Jumps

33. Datapath with Jumps Added!

34. Did you see how the branches and Jumps are implemented in a MIPS?
By the way, did you see any problem with the
previous datapath implementation?

35. Performance Issues Longest delay determines clock period
Critical path: load instruction
Instruction memory  register file  ALU  data memory  register file
Not feasible to vary period for different instructions
We will improve performance by pipelining

36. MIPS Pipelined Datapath
Need registers between stages
To hold information produced in previous cycle

37. Let’s Add Jumps and Branches to our
Microprogrammed SM

38. Adding Jumps to Microprogrammed SM
Controller should be capable of jumping to start generating control signals from a new address in the PM.
Make branching address part of micro-code !
Unconditional Branching

39. Program Counter based Controllers
Like we discussed in MIPS datapath!

40. Wrap-up

41. THANK YOU