1. 时序电路 Digital Circuits 刘鹏 liupeng@zju.edu.cn 浙江大学信息与电子工程系 信息与通信工程研究所
EE141
时序电路 Digital Circuits 刘鹏
浙江大学信息与电子工程系
信息与通信工程研究所
Mar. 22, 2012
Winter ZDMC – Lec. #1 – 1

2. 复习 时序逻辑电路 时序电路通常包含组合电路和存储电路两部分.
EE141
时序逻辑电路 复习
时序电路通常包含组合电路和存储电路两部分.
存储电路的输出状态反馈到组合电路的输入端，与输入信号一起，共同决定组合逻辑电路的输出.
任一时刻的输出信号不仅取决于当时的输入信号，还取决于电路原来的状态（与以前的输入有关）.
组合逻辑电路
存储电路
输出方程Yi
驱动方程Zi
状态方程 Qi
输入Xi
时序电路的结构框图
Winter ZDMC – Lec. #1 – 2

3. 复习 FSM:有限状态机 采用输入信号和电路状态的逻辑函数去描述时序电路逻辑功能的方法 Mealy型 Moore型
EE141
FSM:有限状态机 复习
采用输入信号和电路状态的逻辑函数去描述时序电路逻辑功能的方法
Mealy型
输出信号取决于存储电路状态和输入变量
Moore型
输出只是存储电路现态的函数
输出与时钟同步
inputs
Moore outputs
Mealy outputs
next state
current state
combinational
logic
Winter ZDMC – Lec. #1 – 3

4. 复习 同步时序电路分析方法 目的是找出电路状态和输出信号的变换规律，指出其逻辑功能 时序 电路 求激励方程 由特征方程 求状态表 画波形图
EE141
同步时序电路分析方法 复习
目的是找出电路状态和输出信号的变换规律，指出其逻辑功能 时序 电路
求激励方程
和输出方程
由特征方程
求状态方程
求状态表
画状态图
画波形图
功能描述
Winter ZDMC – Lec. #1 – 4

5. 74LS 194A， 左/右移，并行输入，保持，异步置零等功能
EE141 复习
74LS 194A， 左/右移，并行输入，保持，异步置零等功能
Winter ZDMC – Lec. #1 – 5

6. EE141
4位双向移位寄存器74LS194A的逻辑图 复习
Winter ZDMC – Lec. #1 – 6

7. EE141
扩展应用（4位 位） 复习
Winter ZDMC – Lec. #1 – 7

8. Shift Register: DFF and JK FF
EE141 复习
Shift Register: DFF and JK FF
Winter ZDMC – Lec. #1 – 8

9. Universal Shift Register
EE141
Universal Shift Register
Holds 4 values
Serial or parallel inputs
Serial or parallel outputs
Permits shift left or right
Shift in new values from left or right
left_in
left_out
right_out
clear
right_in
output
input s0 s1
clock
clear sets the register contents and output to 0 s1 and s0 determine the shift function s0 s1 function hold state shift right shift left load new input
Winter ZDMC – Lec. #1 – 9

10. Design of Universal Shift Register
EE141
Design of Universal Shift Register
Consider one of the four flip-flops
New value at next clock cycle:
Nth cell
to N-1th cell
to N+1th cell Q D
CLK
clear s0 s1 new value 1 – – output output value of FF to left (shift right) output value of FF to right (shift left) input
CLEAR
s0 and s1 control mux 1 2 3
Q[N-1] (left)
Q[N+1] (right)
Input[N]
Winter ZDMC – Lec. #1 – 10

11. Shift Register Holds samples of input
EE141
Shift Register
Holds samples of input
Store last 4 input values in sequence
4-bit shift register: D Q IN
OUT1
OUT2
OUT3
OUT4
CLK
Winter ZDMC – Lec. #1 – 12

12. Shift Register Verilog
EE141
Shift Register Verilog
module shift_reg (out4, out3, out2, out1, in, clk);
output out4, out3, out2, out1;
input in, clk;
reg out4, out3, out2, out1;
clk)
begin
out4 <= out3;
out3 <= out2;
out2 <= out1;
out1 <= in;
end
endmodule
Winter ZDMC – Lec. #1 – 13

13. Shift Register Verilog
EE141
Shift Register Verilog
module shift_reg (out, in, clk);
output [4:1] out;
input in, clk;
reg [4:1] out;
clk)
begin
out <= {out[3:1], in};
end
endmodule
Winter ZDMC – Lec. #1 – 14

14. Register with selective load
EE141
Register with selective load
We often use registers to hold values for multiple clocks
Wait until needed
Used multiple times
How do we modify our D flip-flop so that it holds the value till we are done with it?
A very simple FSM
En State Next
Q Q
Q D D Q D Q
clk
enable
enable
clk
Winter ZDMC – Lec. #1 – 15

15. Universal Shift Register
EE141
Universal Shift Register
Holds 4 values
Serial or parallel inputs
Serial or parallel outputs
Permits shift left or right
Shift in new values from left or right
left_in
left_out
right_out
clear
right_in
output
input s0 s1
clock
clear sets the register contents and output to 0 s1 and s0 determine the shift function s0 s1 function hold state shift right shift left load new input
Winter ZDMC – Lec. #1 – 16

16. Design of Universal Shift Register
EE141
Design of Universal Shift Register
Consider one of the four flip-flops
New value at next clock cycle:
Nth cell
to N-1th cell
to N+1th cell Q D
CLK
clear s0 s1 new value 1 – – output output value of FF to left (shift right) output value of FF to right (shift left) input
CLEAR
s0 and s1 control mux 1 2 3
Q[N-1] (left)
Q[N+1] (right)
Input[N]
Winter ZDMC – Lec. #1 – 17

17. Universal Shift Register Verilog
EE141
Universal Shift Register Verilog
module univ_shift (out, lo, ro, in, li, ri, s, clr, clk);
output [3:0] out;
output lo, ro;
input [3:0] in;
input [1:0] s;
input li, ri, clr, clk;
reg [3:0] out;
assign lo = out[3];
assign ro = out[0];
clk or clr)
begin
if (clr) out <= 0;
else
case (s)
3: out <= in;
2: out <= {out[2:0], ri};
1: out <= {li, out[3:1]};
0: out <= out;
endcase
end
endmodule
Winter ZDMC – Lec. #1 – 18

18. EE141
4位双向移位寄存器74LS194A的逻辑图
Winter ZDMC – Lec. #1 – 19

19. Shift Register Application
EE141
Shift Register Application
Parallel-to-serial conversion for serial transmission
parallel outputs
parallel inputs
serial transmission
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20. Pattern Recognizer Combinational function of input samples
EE141
Pattern Recognizer
Combinational function of input samples
In this case, recognizing the pattern 1001 on the single input signal D Q IN
OUT1
OUT2
OUT3
OUT4
CLK
OUT
Winter ZDMC – Lec. #1 – 21

21. Another Example Door combination lock:
EE141
Another Example
Door combination lock:
punch in 3 values in sequence and the door opens; if there is an error the lock must be reset; once the door opens the lock must be reset
inputs: sequence of input values, reset
outputs: door open/close
memory: must remember combination or always have it available as an input
Winter ZDMC – Lec. #1 – 22

22. Implementation in Software
EE141
Implementation in Software
integer combination_lock ( ) {
integer v1, v2, v3;
integer error = 0;
static integer c[3] = 3, 4, 2;
while (!new_value( ));
v1 = read_value( );
if (v1 != c[1]) then error = 1;
v2 = read_value( );
if (v2 != c[2]) then error = 1;
v3 = read_value( );
if (v2 != c[3]) then error = 1;
if (error == 1) then return(0); else return (1); }
Winter ZDMC – Lec. #1 – 23

23. Implementation as a Sequential Digital System
EE141
Implementation as a Sequential Digital System
Encoding:
how many bits per input value?
how many values in sequence?
how do we know a new input value is entered?
how do we represent the states of the system?
Behavior:
clock wire tells us when it’s ok to look at inputs (i.e., they have settled after change)
sequential: sequence of values must be entered
sequential: remember if an error occurred
finite-state specification
reset
value
open/closed
new
clock
state
Winter ZDMC – Lec. #1 – 24

24. Sequential Example: Abstract Control
EE141
Sequential Example: Abstract Control
Finite-state diagram
States: 5 states
represent point in execution of machine
each state has outputs
Transitions: 6 from state to state, 5 self transitions, 1 global
changes of state occur when clock says it’s ok
based on value of inputs
Inputs: reset, new, results of comparisons
Output: open/closed
ERR
closed
C1!=value & new
C2!=value & new
C3!=value & new S1 S2 S3
OPEN
reset
closed
closed
closed
open
C1=value & new
C2=value & new
C3=value & new
not new
not new
not new
Winter ZDMC – Lec. #1 – 25

25. Data-path vs. Control Internal structure data-path control
EE141
Data-path vs. Control
Internal structure
data-path
storage for combination
comparators
control
finite-state machine controller
control for data-path
state changes controlled by clock
new
equal
reset
value C1 C2 C3
mux control
multiplexer
controller
clock
comparator
equal
datapath
open/closed
Winter ZDMC – Lec. #1 – 26

26. Sequential Example :Finite-State Machine
EE141
Sequential Example :Finite-State Machine
Finite-state machine
refine state diagram to include internal structure
closed
mux=C1
reset
equal & new
not equal & new
not new S1 S2 S3
OPEN
ERR
mux=C2
mux=C3
open
Winter ZDMC – Lec. #1 – 27

27. Sequential Example: Finite-State Machine
EE141
Sequential Example: Finite-State Machine
Finite-state machine
generate state table (much like a truth-table)
closed
mux=C1
reset
equal & new
not equal & new
not new S1 S2 S3
OPEN
ERR
mux=C2
mux=C3
open
Symbolic states
reset new equal state state mux open/closed 1 – – – S1 C1 closed 0 0 – S1 S1 C1 closed S1 ERR – closed S1 S2 C2 closed 0 0 – S2 S2 C2 closed S2 ERR – closed S2 S3 C3 closed 0 0 – S3 S3 C3 closed S3 ERR – closed S3 OPEN – open 0 – – OPEN OPEN – open 0 – – ERR ERR – closed
next
Encoding?
Winter ZDMC – Lec. #1 – 28

28. Sequential Example: Encoding
Encode state table
state can be: S1, S2, S3, OPEN, or ERR
needs at least 3 bits to encode: 000, 001, 010, 011, 100
and as many as 5: 00001, 00010, 00100, 01000, 10000
choose 4 bits: 0001, 0010, 0100, 1000, 0000
Encode outputs
output mux can be: C1, C2, or C3
needs 2 to 3 bits to encode
choose 3 bits: 001, 010, 100
output open/closed can be: open or closed
needs 1 or 2 bits to encode
choose 1 bits: 1, 0
binary
One-hot
hybrid
Winter ZDMC – Lec. #1 – 29

29. Sequential Example :Encoding
Encode state table
state can be: S1, S2, S3, OPEN, or ERR
choose 4 bits: 0001, 0010, 0100, 1000, 0000
output mux can be: C1, C2, or C3
choose 3 bits: 001, 010, 100
output open/closed can be: open or closed
choose 1 bits: 1, 0
reset new equal state state mux open/closed 1 – – – – – – – – – – – – – – – – 0
next
good choice of encoding!
mux is identical to last 3 bits of next state open/closed is identical to first bit of state
Winter ZDMC – Lec. #1 – 30

30. Sequential Example : Controller Implementation
EE141
Sequential Example : Controller Implementation
Implementation of the controller
special circuit element, called a register, for remembering inputs
when told to by clock
new
equal
reset
mux control
controller
clock
new
equal
reset
open/closed
mux control
comb. logic
clock
state
open/closed
Winter ZDMC – Lec. #1 – 31

31. One-hot Encoded FSM Even Parity Checker Circuit: In General:
EE141
One-hot Encoded FSM
Even Parity Checker Circuit:
In General:
FFs must be initialized for correct operation (only one 1)
Winter ZDMC – Lec. #1 – 32

32. FSM Implementation Notes
EE141
FSM Implementation Notes
General FSM form:
All examples so far generate output based only on the present state:
Commonly called Moore Machine
(If output functions include both present state and input then called a Mealy Machine)
Winter ZDMC – Lec. #1 – 33

33. Design Hierarchy system data-path control code registers
EE141
Design Hierarchy
system
data-path
control
code registers
state registers
combinational logic
multiplexer
comparator
register
logic
switching networks
Winter ZDMC – Lec. #1 – 34