1. UNIT-VII Advanced Micro Processors Introduction to 80286
Salient Features of 80386
Real and Protected Mode
Segmentation & Paging
Salient Features of Pentium
Overview of RISC Processors.

2. Features of 80286 80286 16 bit µp 16 Mbytes physical memory Multi-user
Multitasking OS
User protection
Virtual memory management

3. 80286 Architecture The bus unit – BU
Performs all memory and i/o reads and writes, pre-fetches instruction bytes and controls transfer of data to and from processor extension devices such as the math coprocessor.
The instruction unit – IU
IU fully decodes up to three pre-fetched instructions and holds them in a queue, where the execution unit can access them.
Instructions in the pipeline
The execution unit – EU
Machine Status Word (MSW) register
The address unit – AU
AU computes the physical addresses that will be sent out to memory or I/O by the BU.
Real address mode
protected virtual address mode
CS, DS, SS, ES registers

4. Fig 7.1 Intel 80286 architecture

5. Register organization
Eight 16-bit GPRs
AX, BX, CX, DX, BP, SP, SI, DI
Four 16-bit segment regs.
DS, CS, SS, ES.
Status and control reg.
Flag reg.
Instruction pointer (IP)

6. Fig 7.2 Machine status word
O – Overflow Flag TS – Task switch
D – Direction EM – Emulate processor extension
I – Interrupt Flag MP – Monitor processor extension
T – Trap Flag PE – Protection enable
S – Sign Flag NT – Nested task flag
Z – Zero Flag IO
Ac – Auxiliary Carry Flag PL
P – Parity Flag
Cy – Carry Flag
X – Not used X NT IO PL O D I T S Z Ac P Cy TS EM MP PE
Fig 7.2 Machine status word
I/O privilege level

7. Interrupts of 80286 Divide error exception - 0
Single step interrupt - 1
NMI interrupt - 2
Break-point interrupt - 3
INTO detected overflow exception
BOUND range exceeded exception – 5
Invalid opcode exception - 6
Processor extension not available (ESC or WAIT)exception
Inter reserved, do not use
Processor extension error interrupt (ESC or WAIT)Inter reserved, do not use
User Defined

8. Maskable Interrupt INTR
Non-maskable Interrupt NMI
Single Step Interrupt
Interrupt Priorities
Order Interrupt
Instruction exception
Single step
NMI
Processor extension segment overrun
INTR
INT instruction

9. 80286 Real Address Mode Operation
After the is reset, it starts executing in its real address mode.
MS-DOS systems operates in Real Address Mode
In this mode can address up to 1MB of physical memory.
Interrupt Vector Table of the is located in the first 1KB of memory. (from address 00000h to 003FFh ).
The addresses from FFFF0h to FFFFFh are reserved for system initialization.
Functions performed in this mode:
It initializes the IP and other registers of 80286
Initializes the peripheral
Enables interrupts
Sets up descriptor tables
Prepares for entering the protected virtual address mode.

10. Protected Virtual Address Mode Operation (PVAM)
The is able to address 1Gbyte if virtual memory per task.
Swapping
Unswapping
Program is divides into Segments or pages
Segments or pages have been associated with a data structure called as a descriptor.
Descriptor contains
segment base address,
segment limit,
segment type,
privilege level,
segment availability in physical memory,
descriptor type and
segment use by another task.
Descriptor table.

11. Descriptors and Their Types
Special types of descriptors which are used to carry out additional functions like
Transfer of control
Task switching
Data segment descriptors
System segment descriptors
Store system data and execution state of a task for multitasking system.
Gate descriptors
The gate descriptors control the access to entry points of the code to be executed.
Interrupt descriptors
These are used to store task gates, interrupt gates and trap gates.
Segment descriptor cache registers: 6-Byte format
Local and Global descriptor table: LDTs & GDTs are 8K array.

12. Privilege
The supports a four level hierarchical privilege mechanism to control the access to descriptors to prevent
unwanted access to any of the code or data segments.
Unintentional interference in the higher privilege level tasks.
(level 0 is the most privilege level while level 4 is the least)
The privilege levels provide protection within a task.

13. Protection
The supports three basic mechanisms to provide protection:
Restricted use of segments (segment load check):
This is accomplished with the help of read/write privileges. The segment usages are restricted by classifying the corresponding descriptors under LDT and GDT.
Restricted Accesses to Segment (operation reference check):
This is accomplished using descriptor usages limitations and the rules of privilege check
Privileged Instructions or Operations (privileged instruction check):
These are to be executed or carried out at certain privilege levels determined by current privilege level (CPL) and I/O privilege level (IOPL) as defined by the flag register.

14. Special Operations Processor reset and initialization
The processor is reset by applying a high on RESET input that terminates all execution and internal bus activities till RESET remains high.
Task switch operation
A no. of task allocation strategies like FCFS, STF, Time sharing, etc.
In case of time sharing, the CPU’s time is divided into equal duration slices.
The switch-over operation from one task to another is called as task switch operation.
This operation is carried out using a JMP or CALL to a new segment of the new task.
Pointer testing instructions
The pointer testing instructions of use the memory management hardware to verify whether the loaded selector value refers to a valid segment without generating any exception.

15. Protected mode initialization
The initialization of protected mode is carried out in real mode by setting the internal registers of suitably.
To enter into protected mode, executes LMSW (load MSW) instruction that set PE flag.
How to enter protected mode?
The execution of instruction LIDT (load interrupt descriptor table base) prepares the for protected virtual address mode.
Then the PE flag of MSW is set to enter the PVAM, using the LMSW instruction.
Halt
This instruction stops program execution and prevents the CPU from restarting, till it is interrupted or RESET is asserted.
If the CPU is interrupted in the HALT state, the execution starts from the next instruction after HLT.

16. 80286 Bus Interface
The I/O devices are also addressed using even and odd address banks technique, using A0 and BHE.
The bus cycles are of six types
Memory read
Memory write
I/O read
I/O write
Interrupt acknowledge
Halt.
The bus at a particular instant may be in either of these four states:
Idle state (Ti)
Perform command state (Tc)
Send status state (Tc)
Hold state (TH)

17. 80386 µp 32-bit µp 4 GB physical memory 16K - segment size
Page size – 4KB
8 debug registers DR0-DR7
80386 has an on-chip address translation
80386DX
132 pins, 20MHz, 33MHz
80386SX
16-bit data bus
24-bit address bus

18. Fig 7.3 Architecture of 80386

19. 1. Central Processing Unit (CPU)
Execution Unit
8 – General Purpose Registers
8 – Special Purpose Registers
Instruction Unit
16-byte instruction code queue
3-byte instruction decoded queue
The barrel shifter increases the speed of all shift and rotate operations

20. 2. Memory Management Unit (MMU)
Segment Unit
4-GB size of segment
Segment and offset for relocability
SU provides a 4 level protection mechanism for protection and isolating the system’s code and data.
Page Unit
Each segment is further divided into pages
4KB- page size
Page Unit works under Segment Unit
It converts linear address into physical address
3. Bus Control Unit (BCU)
Bus control unit had a prioritizer to resolve the priority of the various bus requests.

21. Fig 7.4 Register organization of 80386

22. Fig 7.5 FLAG Register
VM Flag : If this is set, enters the virtual 8086 mode within the protected mode
RF-Resume flag : This is used with the debug register breakpoints, i.e. any debug fault is ignored during the instruction cycle.

23. Modes REAL MODE After reset FFFF FFF0h under the RAM
Interrupt Vector table – FFh -- 1KB
PROTECED MODE
4-GB --- PA
64-TB --- virtual memory/task

24. Fig 7.6 Physical address formation in Real Mode of 80386

25. Fig 7.7 Physical Address formation in Protected mode

26. Fig 7.8 Paging operation in Virtual mode

27. Fig 7.9 Paging unit enabled in protected mode

28. Pentium Processor
The Pentium processor has 237 pins, arranged in a pin grid array (PGA)
64 pins are data pins --- D0-D63
8 pins are parity --- DP0-DP7
Parity errors are indicated by these pins
Address bus (with parity check bit) --- A3-A31
BE0-BE7: are used to select the eight memory banks to accomplish an 8-byte data transfer

29. Fig 7.10 Pentium CPU Architecture

30. Fig 7.11 Superscalar Organization

31. RISC Processors RISC: Reduced Instruction Set Computer CISC :
complex instructions
Increase in processor die size
Consumes more power and silicon
Needs more cooling arrangement.
RISC:
Small, highly optimized set of instructions
Every instruction is executed in a single clock after it is fetched and decoded.
Very fast execution
Less power consumption

32. The Advantages of RISC
RISC instructions, being simple, can be hard-wired
Processor can work at a high clock frequency and thus yields higher speed.
On-chip MMU, Floating point arithmetic units.
Chip cost is low
More devises can place on chip
Compilers produce more efficient codes in RISC µp
Loading and decoding of instructions in a RISC processor is simple and fast.

33. Design issues of RISC processor
Register Windowing
Massive Pipelining
Single cycle instruction execution
Some RISC processors
1. MIPS
2. Sun Ultra SPARC