1. Lecture 13 PicoBlaze I/O & Interrupt Interface
ECE 448 – FPGA and ASIC Design with VHDL

2. ECE 448 – FPGA and ASIC Design with VHDL
Required reading
P. Chu, FPGA Prototyping by VHDL Examples
Chapter 16, PicoBlaze I/O Interface
Chapter 17, PicoBlaze Interrupt Interface
ECE 448 – FPGA and ASIC Design with VHDL

3. Output Decoding of Four Output Registers
ECE 448 – FPGA and ASIC Design with VHDL

4. Timing Diagram of an Output Instruction
ECE 448 – FPGA and ASIC Design with VHDL

5. Truth Table of a Decoding Circuit
ECE 448 – FPGA and ASIC Design with VHDL

6. Block Diagram of Four Continuous-Access Ports
ECE 448 – FPGA and ASIC Design with VHDL

7. Timing Diagram of an Input Instruction
ECE 448 – FPGA and ASIC Design with VHDL

8. Block Diagram of Four Single-Access Ports
ECE 448 – FPGA and ASIC Design with VHDL

9. ECE 448 – FPGA and ASIC Design with VHDL
FIFO Interface
clk
rst
clk
rst
FIFO
din
dout 8 8
full
empty
write
read
ECE 448 – FPGA and ASIC Design with VHDL

10. ECE 448 – FPGA and ASIC Design with VHDL
Operation of FIFO
ECE 448 – FPGA and ASIC Design with VHDL

11. ECE 448 – FPGA and ASIC Design with VHDL
Interrupt Flow
ECE 448 – FPGA and ASIC Design with VHDL

12. Timing Diagram of an Interrupt Event
ECE 448 – FPGA and ASIC Design with VHDL

13. ECE 448 – FPGA and ASIC Design with VHDL

14. Interrupt Interface with a Single Event
ECE 448 – FPGA and ASIC Design with VHDL

15. Interrupt Interface with Two Requests
ECE 448 – FPGA and ASIC Design with VHDL

16. Time-Multiplexed Seven Segment Display
ECE 448 – FPGA and ASIC Design with VHDL

17. Block Diagram of the Hexadecimal Time-Multiplexing Circuit
ECE 448 – FPGA and ASIC Design with VHDL

18. ECE 448 – FPGA and ASIC Design with VHDL
Hexadecimal Multiplexing Circuit Based on PicoBlaze and mod-500 Counter
ECE 448 – FPGA and ASIC Design with VHDL