1. Chapter 5 Basic Computer Organization and Design
충남대학교 컴퓨터전공
이 철 훈

2. Chapter 5
Instruction Codes
컴퓨터 구조는 그 컴퓨터가 사용하는 내부 registers, timing and control structure, 그리고 instruction set으로 정의
Instruction code는 컴퓨터로 하여금 특정 operation을 하라고 지시하는 bit group이다
Instruction code = operation code (Opcode) + address part
Operation code : operation 을 지정
Address part : operation에 사용될 operand가 있는 주소
Addressing modes
Immediate addressing : instruction code 중 address bit들이 operand의 주소가 아니고 operand 그 자체임
direct addressing : operand = M [address]
Indirect addressing : operand = M [M [address]]
Computer System Architecture 1

3. Fig. 5-2 Demonstration of direct and indirect address
Chapter 5
Instruction Codes
Fig Demonstration of direct and indirect address
Computer System Architecture 1

4. Fig. 5-3 Basic computer registers and memory
Chapter 5
Computer Registers
Basic computer registers and memory
Fig Basic computer registers and memory
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5. Fig. 5-4 Basic computer registers connected to a common bus
Chapter 5
Computer Registers
Common bus system
Computer System Architecture 1
Fig Basic computer registers connected to a common bus

6. Computer Instructions
Chapter 5
Computer Instructions
Basic computer의 3가지 기본 instruction format
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7. Computer Instructions
Chapter 5
Computer Instructions
Basic computer instructions
Computer System Architecture 1
Tab Basic computer instructions

8. Computer Instructions
Chapter 5
Computer Instructions
Computer가 다음의 4가지 category에 해당하는 각각의 충분한 instruction들을 가지고 있을 때, 그 instruction set은 complete하다고 한다.
1. arithmetic, logic, and shift instructions
2. instruction for moving information to and from memory and processor registers
3. program control instruction together with instruction that check status conditions input and output instructions
Computer System Architecture 1
Tab Basic computer instructions

9. Tab. 5-2 Basic computer instructions
Chapter 5
Timing and Control
Basic computer의 모든 register에 대한 timing은 master clock generator가 제공하는 clock pulse에 의해 control된다.
Register 내용은 control signal에 의해 enable되어 있을 경우에만 clock pulse에 의해 바뀐다.
Control signal은 control unit에 의해 generate된다.
Control unit
Hardwired control : control logic이 gate, flip-flop, decoder, 또는 다른 logic circuit으로 구성된다
Microprogrammed control : control 정보가 control memory에 저장
Hardwired control은 속도가 빠른 대신 수정이 어렵다.
Computer System Architecture 1
Tab Basic computer instructions

10. Fig. 5-6 Control unit of basic computer
Chapter 5
Timing and Control
Block diagram of control unit
Computer System Architecture 1
Fig Control unit of basic computer

11. Fig. 5-7 Example of control timing signals
Chapter 5
Timing and Control
Timing signal : sequence counter는 timing signal을 generate한다.
D3T4 : SC ← 0 : D3 = T4 = 1이면, CLR = 1로 하여 SC를 set한다.
Fig Example of control timing signals
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12. Fig. 5-6 Control unit of basic computer
Chapter 5
Instruction Cycles
각 instruction cycle은 다음과 같은 subcycle로 나뉘어 진다.
1. fetch an instruction from memory
2. decode the instruction
3. read the effective address from memory in indirect addressing mode
4. execute the instruction
Fetch and Decode
T0 : AR ← PC
T1 : IR ← M [AR ], PC ← PC + 1
T2 : D0,…, D7 ← decode IR (12 – 14), AR ← IR (0 -11), I ← IR (15)
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Fig Control unit of basic computer

13. Fig. 5-8 Register transfer for the fetch cycle
Chapter 5
Instruction Cycles
Computer System Architecture 1
Fig Register transfer for the fetch cycle

14. Fig. 5-9 Flowchart for instruction cycle (initial configuration)
Chapter 5
Instruction Cycles
Determine the type of instruction
D’7IT3 : AR ← M [AR ]
D’7I’T3 : Nothing
D7I’T3 : Execute a register-transfer instruction
D7IT3 : Execute an input-output instruction
Computer System Architecture 1
Fig Flowchart for instruction cycle (initial configuration)

15. Tab. 5-3 Execution of Register-reference instructions
Chapter 5
Instruction Cycles
Register-reference instructions
Tab Execution of Register-reference instructions
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16. Memory-Reference Instructions
Chapter 5
Memory-Reference Instructions
BSA : Branch and Save Return Address (subroutine call)
D5T4 : M [AR ] ← PC, AR ← AR + 1
D5T5 : PC ← AR, SC ← 0
⇒ indirect BUN instruction at the end of the subroutine performs the function refered to as a subroutine return
Fig Example of BSA instruction execution
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17. Memory-Reference Instructions
Chapter 5
Memory-Reference Instructions
Memory-reference instruction control flowchart
Fig Flowchart for memory-reference instructions
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18. Input-Output and Interrupt
Chapter 5
Input-Output and Interrupt
Input-output operations
Programmed control transfer : inefficient!!
Interrupt
Flowchart for interrupt cycle (R : interrupt flip-flop)
If R = 0
∗ RT0 : AR ← 0, TR ← PC
∗ RT1 : M [ AR ] ← TR, PC ← 0
∗ RT2 : PC ← PC + 1, IEN ← 0, R ← 0, SC ← 0
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19. Input-Output and Interrupt
Chapter 5
Input-Output and Interrupt
Fig Flowchart for interrupt cycle
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20. Input-Output and Interrupt
Chapter 5
Input-Output and Interrupt
Demonstration of the interrupt cycle
Fig Demonstration of the interrupt cycle
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21. Complete Computer Description
Chapter 5
Complete Computer Description
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Fig Flowchart for computer operation

22. Complete Computer Description
Chapter 5
Complete Computer Description
Tab Control function and µInstructions for the Basic computer
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23. Complete Computer Description
Chapter 5
Complete Computer Description
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24. Design of Basic Computer
Chapter 5
Design of Basic Computer
Control of registers and memory
Control logic of AR
R’T0 : AR ← PC
R’T2 : AR ← IR (0-11)
D’7IT3: AR ← M [ AR ]
RT0 : AR ← 0
D5T4 : AR ← AR + 1
therefore,
LD (AR ) = R’T0 + R’T2 + D’7IT3
CLR (AR ) = RT0
INR (AR ) = D5T4
Memory read operation (symbol ← M [ AR ])
Read = R’T1 + D’0IT3 + (D0 + D1 + D2 + D6)T4
Fig Control gates associated with AR
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25. Design of Accumulator Logic
Chapter 5
Design of Accumulator Logic
Statements and circuits associated with AC
Fig Circuits associated with AC
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26. Design of Accumulator Logic
Chapter 5
Design of Accumulator Logic
Control of AC register
Fig Gate structure for controlling the LD, INR, and CLR of AC
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27. Design of Accumulator Logic
Chapter 5
Design of Accumulator Logic
Adder and logic circuit
Fig One stage of adder and logic circuit
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