1. Lucas Lancellotti Lucas Santana
6.175 Final Project
Lucas Lancellotti
Lucas Santana
Fall 2015

2. Planning Planning Project part 1 coding Project part 1 debugging
11.27
11.28
11.29
11.30
12.01
12.02
12.03
12.04
12.05
12.06
12.07
12.08
12.09 1 2 3 4 5 6
Planning
Project part 1 coding
Project part 1 debugging
Project part 2 units coding
Project part 2 units debugging
Integration

3. Accomplished Planning Project part 1 coding Project part 1 debugging
11.27
11.28
11.29
11.30
12.01
12.02
12.03
12.04
12.05
12.06
12.07
12.08
12.09 1 2 3 4 5 6
Planning
Project part 1 coding
Project part 1 debugging
Project part 2 units coding
Project part 2 units debugging
Integration

4. Design Milestones Part 1 Conflict Solving (Ex1)
Adding Store Queue (Ex2)
LHUSM (Ex3)
Part 2
Message FIFO (Ex1)
Message Router (Ex2)
L1 D Cache (Ex3)
PPP (Ex4)

5. Difficult part 1 Wrong implementation of store queue
Knowledgement of implict guards

6. Difficult part 2 How to handle both cores in Message Router
Understand MSI protocol and translate form slides
Debugging the test from the unit test for Dcache
How to interface the PPP with the Memory (WideMem)

7. Improvements for the course
Textbook
Timing for the Labs and Project
-The textbook is very useful but it does not totally cover the second and most difficult part of the course or it does
-Overlaping time to do the Labs; more time for the project

8. Obrigado!
Oops... Thank you!