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Chapter 05
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Figure 5.1 A simple matrix–matrix multiplication kernel using one thread to compute each d_P element (copied from Figure 4.7).
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Figure 5.2 Overview of the CUDA device memory model.
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Figure 5.3 Memory versus registers in a modern computer based on the von Neumann model.
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Figure 5.4 Shared memory versus registers in a CUDA device SM.
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Figure 5.5 A small example of matrix multiplication. For brevity,
We show d_M[y*Width+x], d_N[y*Width+x], d_P[y*Width + x] as My,x, Ny,x, Py,x, respectively.
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Figure 5.6 Global memory accesses performed by threads in block0,0.
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Figure 5.7 Reducing traffic congestion in highway systems.
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Figure 5.8 Carpooling requires synchronization among people.
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Figure 5.9 Tiled algorithms require synchronization among threads.
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Figure 5.10 Tiling M and N matrices to utilize shared memory.
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Figure 5.11 Execution phases of a tiled matrix multiplication.
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Figure 5.12 Tiled matrix multiplication kernel using shared memory.
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Figure 5.13 Calculation of the matrix indices in tiled multiplication.
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