1. Data Transmission System Digital Design Chris Langley NRAO
Back End & LO PDR
24-25 April 2002
Data Transmission System Digital Design Chris Langley NRAO
Back End Preliminary Design Review, 2002 April 24-25, Granada, Spain
<Title of topic>

2. Data Transmission System - DTS
Back End & LO PDR
24-25 April 2002
Data Transmission System - DTS
Serializes, synchronizes, and transmits digitized baseband data from antenna digitizers to central site
Receives four 48-bit 250 MHz per polarity from digitizers
Transmits 24 Gb/s payload on 3 channels in a single system. Four systems per antenna incorporate twelve optical channels.
Provides continuous Bit-Error-Rate performance monitoring
C. Langley
2/28/2019
Back End Preliminary Design Review, 2002 April 24-25, Granada, Spain
<Title of topic>

3. Data Flow – Digitizers to Correlator
C. Langley
2/28/2019
Back End Preliminary Design Review, 2002 April 24-25, Granada, Spain

4. Back End Preliminary Design Review, 2002 April 24-25, Granada, Spain
I/O Requirements
Inputs
LVDS data in from digitizers
125 MHz sine, +10 dBm from central reference distributor
Hz LVDS from central reference distributor
CAN/Reset bus RS422 from correlator
48VDC
Outputs
LVCMOS data out to correlator
CAN/Reset bus RS422 to correlator
Laser Safe RS422 to EDFA rack
C. Langley
2/28/2019
Back End Preliminary Design Review, 2002 April 24-25, Granada, Spain

5. Back End Preliminary Design Review, 2002 April 24-25, Granada, Spain
DTS Specifications
Bit-Error-Rate (End-of-Life)
Data bit rate per digitizer Gb/s
Data bit rate per antenna Gb/s
Formatted bit rate per antenna Gb/s
Link synchronization loss < 10-4
C. Langley
2/28/2019
Back End Preliminary Design Review, 2002 April 24-25, Granada, Spain

6. Back End Preliminary Design Review, 2002 April 24-25, Granada, Spain
DTS Block Diagram Four transmitter and four receiver modules per antenna
C. Langley
2/28/2019
Back End Preliminary Design Review, 2002 April 24-25, Granada, Spain

7. Single DTS Block Diagram (four units per antenna)
C. Langley
2/28/2019
Back End Preliminary Design Review, 2002 April 24-25, Granada, Spain

8. Data Transmitter Module (DTM)
C. Langley
2/28/2019
Back End Preliminary Design Review, 2002 April 24-25, Granada, Spain

9. Back End Preliminary Design Review, 2002 April 24-25, Granada, Spain
FPGA – Xilinx XCV300E/BG432
1500+ configurable logic blocks
316 I/O’s
Clock management
8 DLLs
Clock multiply and divide
Double data rate applications supported
Differential signaling support
LVDS, LVPECL
Up to 137 differential IO pairs
300+ MHz input clock / 400+ MHz internal clocking
C. Langley
2/28/2019
Back End Preliminary Design Review, 2002 April 24-25, Granada, Spain

10. FPGA – Xilinx XCV300E (continued)
In-circuit programmable
bootstrap
on the fly
“Low” power device
1.8 VDC core
additional 2.5 and 3.3 VDC supply voltages required
C. Langley
2/28/2019
Back End Preliminary Design Review, 2002 April 24-25, Granada, Spain

11. Back End Preliminary Design Review, 2002 April 24-25, Granada, Spain
DTM Regulated Power
48VDC input power
Vicor Powerstick™ Series switching DC – DC converters provide:
Trim up/down capability
1.8, 2.5, and 10A
–5.2VDC and 6.25A
integrated heat sink
integrated monitor and control features
Linear Technology Step Up Converter
3.3VDC to 500 mA
C. Langley
2/28/2019
Back End Preliminary Design Review, 2002 April 24-25, Granada, Spain

12. DTM Monitor and Control
C. Langley
2/28/2019
Back End Preliminary Design Review, 2002 April 24-25, Granada, Spain

13. DTM Digital Multiplexer
Requirements
16:1
LVDS compatible 625 MHz
CML compatible 10 Gb/s
Integrated VCO
Integrated clock multiply unit (PLL) for locking VCO to external reference clock
PLL out of lock (phase error) detection
C. Langley
2/28/2019
Back End Preliminary Design Review, 2002 April 24-25, Granada, Spain

14. DTM Multiplexer: AMCC vs. GIGA (US $)
Power: AMCC S = 2.3W GIGA = 2.2W
AMCC requires additional power sequencing circuitry ($5)
GIGA requires external reference clock device (~ $100/100)
Cost/100: AMCC $499 GIGA < $260
Device evaluation/comparison incomplete
C. Langley
2/28/2019
Back End Preliminary Design Review, 2002 April 24-25, Granada, Spain

15. Eye Pattern – AMCC S3091 Mux (through 22 km fiber)
C. Langley
2/28/2019
Back End Preliminary Design Review, 2002 April 24-25, Granada, Spain

16. Possible Alternative Mux
AMCC S3097
Improved eye pattern
“Drop in replacement” for S3091
Requires additional 2.5VDC supply
Cost/100 $400 US
Available
C. Langley
2/28/2019
Back End Preliminary Design Review, 2002 April 24-25, Granada, Spain

17. Back End Preliminary Design Review, 2002 April 24-25, Granada, Spain
DTM Interfaces
Digitizer to transmitter formatter card
EPT Hardmetric – high speed, optional shielding
Transmitter formatter card to digital multiplexer card
AMP Mictor - 50Ω terminal impedance, high speed, low crosstalk
Digital multiplexer card to fiber optic transmitter card
SRI 3.5mm RF - 50Ω terminal impedance, 34 GHz
Clock generator card to transmitter formatter card
Johnson Components - 50Ω impedance, 12.4 GHz SMA
C. Langley
2/28/2019
Back End Preliminary Design Review, 2002 April 24-25, Granada, Spain

18. DTM DC Power Supply/Demand
VDC =>
-5.2
1.8
2.5
3.3
5.0
12.0
Supplied
6.25A
10A
500mA
Required
0.7A
1A*
210mA 1A
C. Langley
2/28/2019
Back End Preliminary Design Review, 2002 April 24-25, Granada, Spain

19. DTM Formatter Card 381mm X 152.4mm
C. Langley
2/28/2019
Back End Preliminary Design Review, 2002 April 24-25, Granada, Spain

20. Data Receiver Module (DRM)
C. Langley
2/28/2019
Back End Preliminary Design Review, 2002 April 24-25, Granada, Spain

21. Back End Preliminary Design Review, 2002 April 24-25, Granada, Spain
FPGA – Xilinx XC2V1000
1200+ configurable logic blocks
408 I/O’s (328 available)
Clock management
12 digital clock managers
Clock multiply and divide
Double data rate applications supported
Differential signaling support
LVDS, LVPECL
420 MHz internal clock / 800+ Mb/s IO
C. Langley
2/28/2019
Back End Preliminary Design Review, 2002 April 24-25, Granada, Spain

22. FPGA – Xilinx XC2V1000 (continued)
In-circuit programmable
bootstrap
on the fly
“Low” power device
1.5 VDC core
additional 3.3 VDC supply voltage required
C. Langley
2/28/2019
Back End Preliminary Design Review, 2002 April 24-25, Granada, Spain

23. Back End Preliminary Design Review, 2002 April 24-25, Granada, Spain
DRM Regulated Power
48VDC input power
Vicor Powerstick™ Series switching DC – DC converters provide:
Trim up/down capability
1.5 and 10A
–5.2VDC and 12VDC at 6.25A
integrated heat sink
integrated monitor and control features
Linear Technology Step Up Converter
3.3VDC to 500 mA
C. Langley
2/28/2019
Back End Preliminary Design Review, 2002 April 24-25, Granada, Spain

24. DRM Monitor and Control
C. Langley
2/28/2019
Back End Preliminary Design Review, 2002 April 24-25, Granada, Spain

25. DRM Digital Demultiplexer
Requirements
1:16
Integrated clock and data recovery with auto acquisition
LVDS compatible clock and data 625 MHz
CML compatible 10 Gb/s
Integrated VCO
Integrated PLL for locking VCO clock with external reference clock
VCO/reference clock out of lock (phase error) detection
C. Langley
2/28/2019
Back End Preliminary Design Review, 2002 April 24-25, Granada, Spain

26. DRM Demultiplexer: AMCC vs. GIGA (US $)
Presently evaluating AMCC S3092 and GIGA GD16584
Power: AMCC = 2.1W GIGA = 3.3W
AMCC multiplexer requires additional power sequencing circuitry and data termination resistors ($7)
Cost/100 AMCC $499 GIGA < $255
Device evaluation incomplete
C. Langley
2/28/2019
Back End Preliminary Design Review, 2002 April 24-25, Granada, Spain

27. Possible Alternative Demux
AMCC S3098
Partner to S3097
“Drop in replacement” for S3092
Requires additional 2.5VDC supply
Cost/100 $400 US
Available
C. Langley
2/28/2019
Back End Preliminary Design Review, 2002 April 24-25, Granada, Spain

28. Back End Preliminary Design Review, 2002 April 24-25, Granada, Spain
DRM Interfaces
Fiber optic receiver to digital demultiplexer card
SRI 3.5mm RF - 50Ω terminal impedance, 34 GHz
Digital demultiplexer card to receiver deformatter card
AMP Mictor - 50Ω terminal impedance, high speed, low crosstalk
Receiver deformatter card to correlator back plane
EPT Hardmetric – high speed, optional shielding
C. Langley
2/28/2019
Back End Preliminary Design Review, 2002 April 24-25, Granada, Spain

29. DRM DC Power Supply/Demand
VDC =>
-5.2
1.5
3.3
5.0
12.0
Supplied
6.25A
10A
500mA
Required
0.7A
1A*
210mA
10mA
C. Langley
2/28/2019
Back End Preliminary Design Review, 2002 April 24-25, Granada, Spain

30. DRM Stack Up    Air flow   
C. Langley
2/28/2019
Back End Preliminary Design Review, 2002 April 24-25, Granada, Spain

31. DRM Deformatter Card 279.4mm X 233.7mm
C. Langley
2/28/2019
Back End Preliminary Design Review, 2002 April 24-25, Granada, Spain

32. ALMA Correlator Station Bin
C. Langley
2/28/2019
Back End Preliminary Design Review, 2002 April 24-25, Granada, Spain

33. Digital Transmitter and Receiver
C. Langley
2/28/2019
Back End Preliminary Design Review, 2002 April 24-25, Granada, Spain

34. Back End Preliminary Design Review, 2002 April 24-25, Granada, Spain
Work Area
C. Langley
2/28/2019
Back End Preliminary Design Review, 2002 April 24-25, Granada, Spain

35. DTS Digital Design Progress
Eye pattern transmitted through 22 km fiber
Digital pattern transmitted electronically from digital transmitter to digital receiver, data clock recovered
C. Langley
2/28/2019
Back End Preliminary Design Review, 2002 April 24-25, Granada, Spain

36. Back End Preliminary Design Review, 2002 April 24-25, Granada, Spain
Immediate Plans
Continue evaluation of AMCC vs. GIGA
Research alternative digital multiplexers and demultiplexers
Possibly redesign using AMCC S3097/3098
Integrate multiplexer/demultiplexer daughter cards into main transmitter and receiver cards
Evaluate on board DC power requirements, simplify if feasible
Incorporate all needed design changes discovered during trouble shooting Rev 0 assemblies
C. Langley
2/28/2019
Back End Preliminary Design Review, 2002 April 24-25, Granada, Spain