1. Open platform for mixed-criticality applications
WICERT2013
Workshop on Industry-Driven Approaches for Cost-effective Certification of Safety-Critical, Mixed-Criticality Systems
Miguel Méndez
José L. Gutierrez,
David Fernández,
Javier Díaz

2. Javier Díaz (jda@ugr.es) / University of Granada
Index
Introduction & motivation
Platform description
Board description
OS and libraries
Application examples
Conclusions and future work
1-Apr-19
Javier Díaz / University of Granada

3. Introduction: RECOMP PROJECT
RECOMP” Reduced Certification Costs Using Trusted Multi-core Platforms”
As said in website ( “RECOMP will provide reference designs and platform architectures, together with the required design methods and tools, for achieving cost-effective certification and re-certification of mixed-criticality, component based, multicore systems”
1-Apr-19
Javier Díaz / University of Granada

4. Introduction: certification/recertification
Certification of safety-critical systems, a very complex process
Safety case
Design/development procedures
Engineering practices
Trazability, test, evidences,… and much more!
Compositional certification still an open issue!
But utilization of qualified tools and devices with previous success history on safety-critical systems make the certification easier.
1-Apr-19
Javier Díaz / University of Granada

5. Introduction: certification/recertification
Choosing the right partners, a big difference!
If third-party companies could provide good qualification/certification documentation and evidences of their products, life could be much more easy!
But this is not always the case …
Information could not be complete enough or could not be available yet.
Information provided could not fits our needs
Certification not completely rely on our hands
1-Apr-19
Javier Díaz / University of Granada

6. Introduction & Motivation
System elements:
Final application
OS, middleware, libraries, gateware
Board
Components (processor, transceiver, connectors).
Your develop the final application. Others elements could be obtained from third-party companies
Typically, certifiable ICs, OS or middleware are available and ready to use in your design
What about the remaining elements?
1-Apr-19
Javier Díaz / University of Granada

7. Introduction & Motivation
Complete set of reference designs and platform architectures for certification could bridge the gap.
Advantage : better time-to-market
Disadvantages: incorrect match, too high specifications
Is time to market reason enough?
Many initiatives on this direction
Qualified IPs from FPGA vendors
Operative systems
Libraries/middleware ….
Tools
1-Apr-19
Javier Díaz / University of Granada

8. Introduction: Open hardware model
Many initiatives already available, from industrial control, teaching (hobbies) … to particle accelerators
Advantages  many eyes
looking at your design!
Higher safety!
1-Apr-19
Javier Díaz / University of Granada

9. Avionics Computing Platform (ACP)
Seven Solutions, in collaboration with University of Granada and RECOMP partners provides a reference design based on open hardware
The whole electronic design files are available under request to
FPGA gateware, ARM and software OS configuration files and BsPs, applications examples are provided
1-Apr-19
Javier Díaz / University of Granada

10. Avionics Computing Platform (ACP)
ACP characteristics
Modular design (processing board + peripherals one)
ARM microcontroller + Virtex-6 FPGA as processing elements robustness to common cause effects (diversity)
Redundant input and outputs
External watchdogs
Power & temperature monitoring
Target applications domains: industrial and avionics.
1-Apr-19
Javier Díaz / University of Granada

11. Avionics Computing Platform (ACP)+
AION
RSB
ACP
1-Apr-19
Javier Díaz / University of Granada

12. Avionics Computing Platform diagram
1-Apr-19
Javier Díaz / University of Granada

13. AION-RSB PERIPHERALS DETAILS
AION peripherals
Processor connections
FPGA
ARM
Share
External memory Xa Xb
External WatchDog X
Ethernet Port Xc
USB port (OHCI host port and transceiver)
Serial ports (RS232, SPI)
LEDs and buttons
JTAG debug and configuration port
Temp. sensors and FPGA onchip monitor (voltage supply and temp.)
General Purpuse I/O
VCO with PLLx5 and oscillators
The ARM has 64MB of DDR2 and 512MB of Flash, while the FPGA has MB of QDRII RAM and 32MByte of Flash.
Through a FPGA controller. It controls the communication between ARM and FPGA which is done through a 32 bits asynchronous bus that can be customized.
Through the RSB board.
1-Apr-19
Javier Díaz / University of Granada

14. MibroBlaze multicore architecture
1-Apr-19
Javier Díaz / University of Granada

15. Leon-3 multicore architecture
1-Apr-19
Javier Díaz / University of Granada

16. Javier Díaz (jda@ugr.es) / University of Granada
OS and libraries
BsP provided by Seven Solutions (Xilinx MicroBlaze) and UGR (Gaisler-Aeroflex Leon-3)
FreeRTOS, OpenRTOS (includding core-to-core Wittenstein libraries) and PikeOS from Sysgo
1-Apr-19
Javier Díaz / University of Granada

17. Application examples (see demo)
Mixed-Critical Multi-Processor Motor Controller with Capabilities for Runtime Update of Software (based on Danffos Case)
1-Apr-19
Javier Díaz / University of Granada

18. Application examples (see demo)
Mixed-criticality Multi-processor Avionics Platform
1-Apr-19
Javier Díaz / University of Granada

19. Javier Díaz (jda@ugr.es) / University of Granada
Conclusions
ACP is a open platform reference design with two different multicore architectures
A dualcore AMP processor based on MicroBlaze.
A Quadcore SMP processor based on Leon-3.
It allows to study key multicore mechanisms:
Spatial isolation provided by hardware mechanisms as the Flash arbiter on the dualcore MicroBlaze architecture or the RTM module for Leon-3.
Temporal isolation provided by PikeOS on the Quadcore Leon-3 architecture.
Core-to-core communication mechanisms of OpenRTOS.
Design is open and available under request
1-Apr-19
Javier Díaz / University of Granada

20. Javier Díaz (jda@ugr.es)
Questions?
Thanks for your attention
Javier Díaz
1-Apr-19
Javier Díaz / University of Granada