1. Introduction to Verilog http://web. sonoma
Department of Engineering Science ES210L Digital Circuit & Logic Design Lab
References
"Digital Design,” Morris Mano and Michael Ciletti, 5th ed, Pearson, 2012.
MobaXterm

2. HDL = Hardware Description Language
Topics Covered
What is Verilog
Verilog HDL Syntax and Semantics
Environment
Verilog Design File Examples
Verilog Test Bench File Examples
Verilog Installation and Installing MobaXterm
Running Verilog Simulation
HDL = Hardware Description Language

3. What is Verilog
Verilog (IEEE 1364) is a Hardware Description Language (HDL)
HDL is a programming language that uses codes to describe & model digital circuits
VHDL (IEEE 1076) is another example of HDL
Verilog allows to simulate digital circuits and displays the output vs input waveforms and propagation time before building them
Digital circuits can be complex when making ICs
Verilog HDL was designed by Phil Moorby, who later became the Chief Designer for Verilog-XL and the first Corporate Fellow at Cadence Design Systems.
VHDL = Very High Level Hardware Design Language, Virtual Hardware Design Language
Verilog is good at hardware modeling but lacks higher level (programming) constructs. VHDL is popular with (European) FPGA designers because low-level modeling is not required in an FPGA flow.
Cadence makes system design & verification & custom IC tools for electronic hardware.
Verilog HDL originated at Gateway Design Automation company in 1985.
The company was held by Dr. Prabhu Goel, inventor of a test generation algorithm.
Gateway Design Automation grew rapidly with the success of Verilog-XL and was finally acquired by Cadence Design Systems, San Jose, CA in 1989.
IC=integrated circuits

4. Example of a Circuit and Verilog Output View
Verilog Design program
Describes the logic circuit
Test bench program specifies
instances of the inputs

5. Two Verilog Programs Needed
//fig3p37_tb.v (Test bench program)
// Specifies instances of inputs
`timescale 1 ms / 1 us
`include "fig3p37.v"
module fig3p37_tb;
wire D,E;
reg A,B,C;
fig3p37 M1(A,B,C,D,E); //Instance name
initial
begin
A =1'b0; B =1'b0; C =1'b0;
#100
A =1'b1; B =1'b1; C =1'b1;
end
initial #200 $finish;
endmodule
//fig3p37.v (Verilog Design Prog) // Defines the digital circuit module fig3p37 (A,B,C,D,E); output D,E; input A,B,C; wire w1; and G1(w1,A,B); not G2(E,C); or G3(D,w1,E); endmodule

6. Verilog HDL Syntax and Semantics
White spaces are ignored - characters that contain white space:
blanks, tabs, newlines, and form feeds
Case sensitive: Lower case letters are unique from upper case letters
All Verilog keywords are lower case
Identifiers are names used to identify an object
e.g., a register, a function, or a module
A name so that it can be referenced from other places in a description.
Identifiers may contain alphabetic characters, numeric characters, the underscore, and the dollar sign (a−z, A−Z, 0−9, $, or _ )
But must begin with an alphabetic character or the underscore character (a−z, A−Z, or _ )
Can be up to 1024 characters long.
Examples of legal identifiers
data_input mu
clk_input my$clk
i386 A
System tasks are available to handle simple I/O and various design measurement functions during simulation. All system tasks are prefixed with $ to distinguish them from user tasks and functions.

7. Example of Bad and Good Codes
Bad Code (although correct):
module addbit(a,b,ci,sum,co);
input a,b,ci;output sum co;
wire a,b,ci,sum,co;endmodule
Good Code
module addbit ( a, b,
ci, // Carry In
sum,
co; // Carry Out );
input a;
input b;
input ci;
output sum;
output co;
wire a;
wire b;
wire ci;
wire sum;
wire co;-
endmodule

8. Sample Program 1 “hello_world”
//−−−−−−−−−−−−−−−−−−−−−−−−−−
// This is my first Verilog Program
// Design Name: hello_world
// File Name: hello_world.v
// Function: This program prints 'hello world’
// Coder: Deepak
module hello_world ; //
initial begin
$display ( "Hello World by Deepak" );
#10 $finish;
end
endmodule // End of Module hello_world
Green words represent comments
“//” starts a comment line
Blue words represent reserved keywords
Lines 8 & 14 start & end a module
Lines 10 to 13 contains initial block that begin & end the block.
The module gets executed at time=0 (0 ms)
Output of the program is:
Hello World by Deepak

9. Examples of Comments
Single line comments begin with token // and end with a carriage return
Multi Line comments
begin with the token /* and
end with the token */
Number spec notation:
<size in bits>’ <base> <number value>, e.g.,
4’b1010 is a 4-bit binary value 1010
16’h6cda is a 16 bit hex number with value 6cda
8’d40 decimal value 40
/* This is a
Multi line comment
example */
module addbit ( a, b,
ci,
sum,
co);
a=4’b1010
Start with /*
End with */
Concatenate signals using the { } operator
Assign {b[b7:0] ,b[15:8]} =
{a[15:8] ,a[7:0]}; effects a byte
swap

10. Examples of Comments // Input Ports, Single line comment
module example;
input a;
input b;
input ci;
// Output ports
output sum;
output co;
// Data Types
wire a;
wire b;
wire ci;
wire sum;
wire co;
endmodule

11. $ character is a prompt in Verilog
Set Up the Environment
Assuming that you want to have a library folder for es210 for your Verilog files and simulation files on the Cadence server that you have an account.
Open a terminal.
~]$ mkdir es210
~]$ cd es210
We can make a Verilog file fig3p37.v in the es210 folder in cadence server
~]$ es210/fig3p37.v
Cadence Design Systems is an American Electronic Design Automation (EDA) software and engineering services company that produces software and hardware for designing integrated circuits, systems on chips (SoCs) & printed circuit boards.
circuit simulation, is an EDA product for and FPGA designs.
$ character is a prompt in Verilog

12. Your First Verilog Program
A Verilog program describes the digital circuit.
module fig3p37 (A,B,C,D,E);
output D,E;
input A,B,C;
wire w1;
and G1(w1,A,B);
not G2(E,C);
or G3(D,w1,E);
endmodule
fig3p37 is the name of the module
Words in blue are keywords
Declare
fig3p37 or Figure 3.37 in Mano ed 6

13. module....endmodule An example of a Verilog Design program
fig3p37 is the name of the module
Always start the Verilog program
with the keyword pair module…endmodule
The keyword module must always be terminated by the keyword endmodule.
Each line here is a statement.
module fig3p37 (A,B,C,D,E);
output D,E;
input A,B,C;
wire w1;
and G1(w1,A,B);
not G2(E,C);
or G3(D,w1,E);
endmodule

14. Keywords Each statement ends with a semicolon
module fig3p37 (A,B,C,D,E);
output D,E;
input A,B,C;
wire w1;
and G1(w1,A,B);
not G2(E,C);
or G3(D,w1,E);
endmodule
Each statement ends with a semicolon

15. Primitive Gates and, not, or are primitive gates
The output is listed first
The inputs and outpts can be listed in any order
G1 is an instance of the and gate
module fig3p37 (A,B,C,D,E);
output D,E;
input A,B,C;
wire w1;
and G1(w1,A,B);
not G2(E,C);
or G3(D,w1,E);
endmodule
Primitive = basic

16. “assign” keyword
“assign” keyword can also be used to assign a value to the output
It is followed by a Boolean expression
To distinguish arithmetic operators from logical operators,
Verilog uses symbols “&”, “|”, and “~” for AND, OR, and NOT, respectively, e.g.,
Verilog Logical statement
Equivalent statement with “assign”
not (Y, X);
assign Y = ~X
and (C, A, B);
assign C = A & B;
or (F, D, E);
assign F = D | E
and (F, A, B);
or (D, F, C’);
assign D = (A & B)|~C;
assign b[0] = a[0], // an array
b[1] = a[1],
b[2] = a[2],
b[3] = a[3];
Ampersand &
Tilde ~
Vertical bar |
See Examples 4.3, 4.4, and 4.5 in textbook by Mano

17. Your First Verilog Program
Without assign
With assign
module fig3p37 (A,B,C,D,E);
output D,E;
input A,B,C;
wire w1;
and G1(w1,A,B);
not G2(E,C);
or G3(D,w1,E);
endmodule
assign w1 = A & B; //cannot name the gate
assign E = ~C;
assign D = w1 | E;
Declare

18. Table 4.10 Some Verilog HDL Operators
= for logical assign
Equal by value,
e.g., 111=111
Logical state of a variable can be true=“1” or false =“0“
Two variable that are represented by binary numbers can be compared or operated upon bitwise.
Complete list in Table 8.1 &

19. Set Up the Testbench
In addition to Verilog design program, we need a test bench program to define the instances (in time) of inputs that we apply to the circuit to get the outputs

20. Test Bench Module
//fig3p37_tb.v is test bench program file
`timescale 1 ms / 1 us
`include "fig3p37.v"
module fig3p37_tb;
wire D,E;
reg A,B,C;
fig3p37 M1(A,B,C,D,E); //Instance name
initial
begin
A =1'b0; B =1'b0; C =1'b0;
#100
A =1'b1; B =1'b1; C =1'b1;
end
initial #200 $finish;
endmodule
fig3p37_tb is the module name for the test bench program
“tb” indicates test bench
“fig3p37.v” identifies design program with file type “v” below
M1 is the instance of the module, required.
Fig3p37 is the main or associated module name (below)
//fig3p37.v is Verilog Design file module fig3p37 (A,B,C,D,E); output D,E; input A,B,C; wire w1; and G1(w1,A,B); not G2(E,C); or G3(D,w1,E); endmodule

21. Test Bench Module
//fig3p37_tb.v (test bench) file
`timescale 1 ms / 1 us
`include "fig3p37.v"
module fig3p37_tb;
wire D,E;
reg A,B,C;
fig3p37 M1(A,B,C,D,E); //Instance name
initial
begin
A =1'b0; B =1'b0; C =1'b0;
#100
A =1'b1; B =1'b1; C =1'b1;
end
initial #200 $finish;
endmodule
(`) is a back apostrophe before timescale and include
“1 ms” specifies the unit of measurement for delays
“1 us” specifies the precision for which delays are rounded off
In Test Bench program the circuit outputs are declared with keyword wire and inputs with keyword reg
The initial keyword is used with a set of statements that begin executing when the simulation is initialized
begin….end
The statements are executed in sequence from top to bottom
reg = register

22. Test Bench Module //fig3p37_tb.v (test bench) file
`timescale 1 ms / 1 us
`include "fig3p37.v"
module fig3p37_tb;
wire D,E;
reg A,B,C;
fig3p37 M1(A,B,C,D,E); //Instance name
initial
begin
A =1'b0; B =1'b0; C =1'b0;
#100
A =1'b1; B =1'b1; C =1'b1;
end
initial #200 $finish;
endmodule
# specifies the delay in the number of time units
Format for variable: size/’/base/value
e.g., A is one binary bit with a value of 1
# 200 specifies the duration for the display

23. MobaXterm Installation
You should have an account on Cadence/Verilog server by ing
Mr. Shahram Marivani
Insert your flash memory into the Lab PC or your laptop
Go to and click on Resources
Click on Remote Server Access
Follow the instruction of MobaXterm for Windows or MAC computer
MobaXterm opens a Terminal page for Windows7 as in Linux
For Windows, click on MobaXterm
You want to install this application on a flash memory so that you can use it in the lab or any computer including your laptop
MobaXterm initiates a secure shell (ssh) session to communicate with the server
On “Home Edition” page click on “Download now”
Click “Mobaterm Home Edition” and “Download Now”
Select “MobaXterm Home Edition v11.0 (Portable edition)” and download zip file on the flash memory
Double click on the file, select MobaXterm_Personal_v11.0.exe and RUN it
alikujoory$ ssh -Y

24. MobaXterm for Windows
As the MobaXterm window opens, you should see a display as shown
Click Session at left top corner
Select SSH at left top corner
In Remote host, type the IP address in the box
Alis-MacBook-Pro:~ alikujoory$ ssh -Y
A Terminal (Linux) window opens
Login using your Seawolf UserName and Password
At this time you can access/build your Verilog directory & programs
E.g. es210/fig3p37.v
To run enter verilog +gui fig3p37.v

25. XQuartz and Xterm for MacBook
You need to download “XQuartz for MAC”
A Terminal (Linux) page opens
At the promp, type ssh -Y
Enter your Seawolf password
At this time you can access/build your Verilog folders and programs
E.g. es210/fig3p37.v

26. Terminal Display – Example 1
Make a folder for es210 on the Terminal page
Use a Linux editor such as vi to make a verilog design file, e.g., fig3p37.v that describes the desired digital circuit
Then, for fig3p37 circuit shown, the location of the Verilog design file is es210/fig3p37.v
(The verilogsandbox folder in terminal display is removed for simplification)
We need also to make a test bench file that defines the desired instances of inputs to apply to the circuit as es210/fig3p37_tb.v
The figure below shows a typical Terminal display.
Next slide shows the Verilog files

27. Verilog Files for – Example 1 on fig3p37
//fig3p37.v is the design file module fig3p37 (A,B,C,D,E); output D,E; input A,B,C; wire w1; and G1(w1,A,B); not G2(E,C); or G3(D,w1,E); endmodule
//fig3p37_tb.v is the test bench file `timescale 1 ms / 1 us `include "fig3p37.v" module fig3p37_tb; wire D,E; reg A,B,C; fig3p37 M1(A,B,C,D,E); //Instance name initial begin A =1'b0; B =1'b0; C =1'b0; #100 A =1'b1; B =1'b1; C =1'b1; end initial #200 $finish; endmodule
Signals that are driven from within a process (an initial or always block) must be of type reg. Signals that are driven from outside a process must be of type wire. The keyword reg does not necessarily imply a hardware register.

28. Verilog for Simulation – Example 1
Compiling and running the Verilog file can simulate the circuit and display the input and output waveforms related to test bench data in fig3p37_tb.v
To compile the file, TYPE
verilog fig3p37_tb.v
and ENTER
fig3p37.v and fig3p37_tb.v files will be first checked for syntax errors, and
fig3p37.v is processed before the digital waveforms are displayed
The file compilation is complete when there are no errors
To run the program, at the prompt, TYPE verilog +gui fig3p37_tb.v and hit ENTER
Note: There are two ways to compile the files:
Make two separate files (preferred):
fig3p37.v and
one that starts with command `include fig3p37.v followed by the fig3p37_tb.v module, in which case you need to run the fig3p37_tb.v file (see next slide), or
Make one composite file that includes fig3p37_tb.v module followed by the fig3p37.v module (next slide, can skip)

29. Verilog Modules – Example 1
For a composite file,
all “//” characters
must to be removed.

30. The Screen after Compiling fig3p37_tb.v

31. Windows After Running fig3p37_tb.v File – Example 1
1. Go to “Simulation”. Select & click
on “Reinvoke Simulator”.
3. Click on “+” sign to expand
the subfolders & click on the “+” sign
of MI to expand. You will see all the
input/output entries in the right
window. Select all these entries.
4. Go to this icon to “Send selected
objects to the waveform”. The place-
holder of the waveforms for all variables
are displayed in a new screen on right.
5. Change time in “Time A” to 100 ms.
Note that you need to change ussec
scale to msec scale.
2. Click “Yes” on the resulting Reinvoke tab & go to the lower screen.
6. Go to “Simulation”. Select & click
“Run”.

32. Windows After Running fig3p37_tb.v File – Example 1
The waveforms of the input signals and the resulting outputs will be displayed in a window for a range.
To view the waveforms in the desired range, 0-200ms in this example, do the following.
7. Go to “Times” and enter the range
to ms for the waveforms & hit
RETURN.to see all waveforms as shown
8. You can move the vertical line
indicator on the waveforms to left &
right by clicking on these arrows
A = B = C = 0 or 1 1 D E w1

33. Example 2: Simulate the Same Circuit with Different Inputs
// Testbench fig3p37 with different inputs `timescale 1 ms / 1 us `include "fig3p37.v" module fig3p37_tb; wire D,E; reg A,B,C; fig3p37 M1(A,B,C,D,E); //Instance name initial begin A =1'b0; B =1'b0; C =1'b0; #100 A =1'b1; B =1'b1; C =1'b1; #50 end initial #400 $finish; endmodule
// commented module fig3p37 (A,B,C,D,E); // output D,E; // input A,B,C; // wire w1; // and G1(w1,A,B); // not G2(E,C); // or G3(D,w1,E); // endmodule

34. Verilog Modules - Example 2

35. Input and Output Waveforms for Example 2