1. Using Verilog header files
Example: buffbless3d_pkg.vh defines parameters shared between .v files
`define flit_size 32
`define packet_size 4
`define port_num 7
`define mesh_x 4
`define mesh_y 4
`define mesh_z 4
`define timestamp_size 6
`define timestamp_low 0
`define timestamp_high `timestamp_low + `timestamp_size -1
`define dest_addr_size 6
`define dest_addr_low `timestamp_high + 1
`define dest_addr_high `dest_addr_low + `dest_addr_size -1
`define seq_num 4
`define seq_num_low `dest_addr_high + 1
`define seq_num_high `seq_num_low + `seq_num -1
`define L `mesh_x-1 + `mesh_y-1 + `packet_size-1
`define golden_bit `seq_num_high + 1

2. Including .vh file
`include "buffbless3d_pkg.vh" module buffer(clk, rst_n, data_in, data_valid_in, ack_rx, req, dest_addr, stall, data_out); output req; ….. `include "buffbless3d_pkg.vh“ module permnet (data_out_N, data_out_S, data_out_E, data_out_W, data_valid_out_N, data_valid_out_S, data_valid_out_E, data_valid_out_W, flit0_inc, flit1_inc, flit2_inc, flit3_inc, flit0_v, flit1_v, flit2_v, flit3_v, port_out_0, port_out_1, port_out_2, port_out_3, req0, req1, req2, req3, reqL, clk, rst_n, randbit);

3. ROM description (1/2)
module rominfr (data, en, addr); output [3:0] data; input en; input [4:0] addr; reg [3:0] ROM [31:0]; (posedge en) data = ROM[addr];

4. ROM description (2/2)
initial begin ROM[0] = 4’b0001; ROM[1] = 4’b0010; ROM[2] = 4’b0011; ROM[3] = 4’b0100; ROM[4] = 4’b0101; ROM[5] = 4’b0110; ROM[6] = 4’b0111; ROM[7] = 4’b1000; ROM[8] = 4’b1001; ROM[9] = 4’b1010; ROM[10] = 4’b1011; ROM[11] = 4’b1100; ROM[12] = 4’b1101; ROM[13] = 4’b1110; ROM[14] = 4’b1111; ROM[15] = 4’b0001; ROM[16] = 4’b0010; ROM[17] = 4’b0011; ROM[18] = 4’b0100; ROM[19] = 4’b0101; ROM[20] = 4’b0110; ROM[21] = 4’b0111; ROM[22] = 4’b1000; ROM[23] = 4’b1001; ROM[24] = 4’b1010; ROM[25] = 4’b1011; ROM[26] = 4’b1100; ROM[27] = 4’b1101; ROM[28] = 4’b1110; ROM[29] = 4’b1111; ROM[30] = 4’b0000; ROM[31] = 4’b0001; end endmodule

5. DUAL –PORT RAM (1/2)
module v_rams_12 (clk1, clk2, we, add1, add2, di, do1, do2); input clk1; input clk2; input we; input [5:0] add1; input [5:0] add2; input [15:0] di; output [15:0] do1; output [15:0] do2; reg [15:0] ram [63:0]; reg [5:0] read_add1; reg [5:0] read_add2;

6. DUAL –PORT RAM (2/2)
clk1) begin if (we) ram[add1] <= di; read_add1 <= add1; end assign do1 = ram[read_add1]; clk2) begin read_add2 <= add2; assign do2 = ram[read_add2]; endmodule

7. Verilog Tasks Tasks are defined in the module in which they are used.
It is possible to define a task in a separate file and use the compile directive 'include to include the task in the file which instantiates the task.
can include timing delays, like posedge, negedge, # delay and wait.
can have any number of inputs and outputs.
variables declared within the task are local to that task.
The order of declaration within the task defines how the variables passed to the task by the caller are used.
can call another task or function.
tan be used for modeling both combinational and sequential logic.
must be specifically called with a statement, it cannot be used within an expression

8. Verilog Tasks
module simple_task(); task convert; input [7:0] temp_in; output [7:0] temp_out; begin temp_out = (9/5) *( temp_in + 32) end endtask endmodule

9. Verilog Tasks
`include "mytask.v“ module task_calling (temp_a, temp_b, temp_c, temp_d); input [7:0] temp_a, temp_c; output [7:0] temp_b, temp_d; reg [7:0] temp_b, temp_d; (temp_a) begin convert (temp_a, temp_b); end (temp_c) convert (temp_c, temp_d); endmodule

10. Verilog functions
functions are defined in the module in which they are used. It is possible to define functions in separate files and use compile directive 'include to include the function in the file which instantiates the task.
functions can not include timing delays, like posedge, negedge, # delay, which means that functions should be executed in "zero" time delay.
functions can have any number of inputs but only one output.
The variables declared within the function are local to that function. The order of declaration within the function defines how the variables passed to the function by the caller are used.
functions can be used for modeling combinational logic.
functions can call other functions, but can not call tasks.

11. Verilog functions
module simple_function(); function myfunction; input a, b, c, d; begin myfunction = ((a+b) + (c-d)); end endfunction endmodule

12. Verilog functions
`include "myfunction.v" module function_calling(a, b, c, d, e, f); input a, b, c, d, e ; output f; wire f; assign f = (myfunction (a,b,c,d)) ? e :0; endmodule

13. Common Verilog Pitfalls

14. Name inconsistency Compile: error Severity: Trivial
module wrong_name (o, i0, i1, i2);
output o;
input i1, i2, i3;
assign o = i0 & i1 ^ i2;
endmodule

15. Multiple unconditional concurrent assignments
Simulation: ‘X’ value
Synthesis: ERROR: signal is multiply driven
Severity: Serious
module …
assign x = a & b;
...
assign x = b ^ c;
(b or c)
begin
x <= b | c;
end

16. Incomplete sensitivity list
Simulation: Unexpected behavior
Synthesis: Warning: Incomplete sensitivity list
Severity: Serious
Solution: complete sensitivity list
(a or b)
begin
d <= (a & b) | c; //c is missing from sensitivity list!!!
end

17. Not assigning all outputs in combinational always block
Simulation:
Synthesis: Warning: Signal not always assigned, storage may be needed
Severity: Serious
Solution: assign all signals
(a or b or c)
begin
if (c == 0) then
d <= (a & b) | c; //d assigned only first time,
else if (c == 1)
e <= a; //e assigned only second time!!!
end

18. Unassigned signals Simulation: Undefined value (‘U’)
Synthesis: Warning: Signal is never used/never assigned a value
Severity: Moderate
module …
output y;
input input1, input2;
reg s;
assign y = input1 & input2; //s never assigned
endmodule

19. Output not assigned or not connected
Simulation: Undefined
Synthesis: Error: All logic removed from the design
Severity: Serious
module my_module (o, input1, input2);
output o;
input input1, input2;
reg s;
assign s = input1 & input2; //output never assigned
endmodule

20. Using sequential instead of concurrent process
Simulation: Unexpectedly delayed signals
Synthesis: More FFs than expected

21. module my_module (o, input1, input2);
output o;
input input1, input2;
o = input1 & input2; //can’t assign this way
endmodule

22. Using the assign keyword in initial/always blocks
(a or b or c) begin assign d = (a & b) | c; //can’t use assign here end