1. ECE 352 Digital System Fundamentals
Basic Processor Structure
In this presentation, we will look at the structure of a basic processor.

2. Designing Computers 101
Computer’s programming interface is called the instruction set architecture (ISA)
Defines instructions and their operands
At a basic level, the computer architecture is divided into datapath and control
Datapath defined by the set of registers, possible microoperations, and the control interface
The control unit instructs the datapath to perform the needed computations
The datapath may access information in memory in addition to its registers
The Instruction Set Architecture, or ISA, defines the interface between the programmer and the processor hardware. This includes specifying what instructions the processor can execute. In this course, we focus on the processor hardware rather than programming techniques. So we will look at how the processor hardware can execute instructions.
The processor itself is a form of complex finite state machine that can be divided into a datapath and the control. The datapath is the part of the processor that performs operations on data, and is itself defined by the register set, the operations it can perform, and the interface it presents to the control unit. The control unit commands the datapath to perform operations as required based on the instruction that is currently being processed. As it performs operations, the datapath may use information from the register file or memory system, and the operations’ results may be stored in the register file or memory.

3. Example Simple Processor
DATA MEMORY
Here is a high-level example of a simple processor. It consists of three major parts. The control unit includes the Program Counter and a separate memory to hold the instructions. The datapath consists of the register file, the function unit, and multiplexers to direct data to where it needs to go. Finally, it also includes data memory, which is connected to the datapath.
Note that this is a little different than a Von Neumann architecture, which you may have seen before. In a Von Neumann architecture, a single memory holds both instructions and data. This diagram, however, shows a Harvard architecture, where instructions and data are contained in separate memories. We use the Harvard architecture in this example processor, since it simplifies the interface to memory.
CONTROL
Example Simple Processor
DATAPATH

4. Datapath Register file Function unit Includes other connections…
Addressable set of registers
Inputs/outputs of most operations
Function unit
Performs calculations
Calculation type chosen by the control signals
Includes other connections…
To/from mem, etc…
Let’s look at the datapath in more detail. The register file is a key component in the datapath, since the registers it contains will supply the operands for, and be the destination of, most operations. The other major component in the datapath is the function unit, which performs the required calculations based on signals received from the control unit. The datapath also includes connections to the data memory and the control unit.

5. Generic Register File Array of addressable storage registers
Outputs value in one or more register(s), each chosen by large mux with the register address as the mux select
Destination address controls which register is enabled to load data input (if write enabled!)
A register is enabled if the decoder input equals the register’s address AND the write enable (WE) is 1
Each register has a unique address
A register file is an array of storage registers. Each register in the array has a unique code, called an address, which we use to identify which of the registers in the register file we wish to read from or write to. The address is used inside the register file in a couple different ways.
First, we can access the value in a particular register by providing the address of that register. That address is used as the select signal for a mux that chooses between the outputs of all of the registers in the register file.
Second, we use the address to select the register that we wish to write to when we are writing a value into the register file. In this case the address is decoded to create a separate enable signal for each register. However, in order to perform a write, the write enable for the register file must also be asserted.

6. Each cycle, this register file can…
Read from two registers
A address chooses register supplying the A data output
B address chooses register supplying the B data output
Write to one register (the destination register)
D address chooses register that will be enabled to load the destination data IF register file is write enabled
In a given cycle, we can perform multiple simultaneous accesses to the register file in our example processor. We can read from up to two registers by supplying the registers’ addresses on the A and B address inputs. The values stored in the specified registers will then appear on the corresponding A and B data outputs. We can also write a value to one of the registers by supplying its address on the D address input and asserting the write enable signal. This will cause the value on the destination input data signal to be written to our chosen register because that register’s load enable will be asserted as a result.

7. Function Unit
In a processor, one or more function units are typically shared by registers in the register file
The example processor has a single function unit: an Arithmetic Logic Unit
A, B are data inputs
FS specifies the ALU operation
F is the result data
V, C, N, Z are ALU status outputs
Any operation not directly supported by the ALU must be calculated using a sequence of supported ALU operations!
Next let’s look at the function unit. Processors usually have one or more function units that are shared by all registers. These are the hardware structures that perform the data processing within the processor.
An ALU is common type of function unit, and our example processor has one of these. It receives two data inputs: A and B, and a control input FS that specifies the operation that the ALU should perform on its input data. The F data output is the result of the ALU operation. The ALU also produces several status signals that indicate information about the ALU operation that is being performed, such as whether the result is zero, or the operation overflowed. These signals can be used by the control unit to determine whether a conditional branch instruction should be taken or not.
If the processor is required to perform operations not supported by the ALU, then it must perform them using a sequence of ALU operations. For example, the ALU in this processor does not support multiplication, but a multiply can be performed by repeated addition. Note that in this example, the ALU is purely combinational, but in reality ALUs are often pipelined to improve performance.

8. Memory Similar in idea to the register file, but…
There are many more “locations”
More bits required for the address
Operations can be much longer latency
Memory is further than the register file from the datapath
Decoding the address takes longer
In our simple model…
Memory can only do one write or one read in a single cycle (but not both)
The register file can do up to two reads (A and B) and one write (D) in a single cycle
DATA MEMORY
The datapath also interfaces to data memory. We can think of this as being similar to the register file, but with significantly more locations. This means a memory address has a far greater bitwidth than does a register address.
For a number of reasons, memory operations generally have MUCH longer latency than register file operations. For example, the memory is physically and electrically further away, decoding the wider address takes more time, and the memory technologies themselves are simply not as fast to respond. The fact that there are more locations also means that the decoder and multiplexing logic is significantly larger than in a register file. So, often a memory is more limited than a register file in terms of the number of simultaneous accesses.
In our particular example processor model, the memory can only do a single memory read or write operation at a time, whereas the smaller register file can simultaneously read up to two values and write one value.

9. Datapath Operation
The datapath completes a single microoperation during each clock cycle
True for our processor… another advanced topic…
Even when it is not true, that is usually hidden from the programmer
The control unit must configure the datapath to make it perform the desired operation
Source operand location(s)
Register file, immediate data, and/or memory
Destination location
Register file or memory
Function unit operation (if used)
In the example processor, we assume that the datapath completes a single microoperation during each clock cycle. In real processors, the datapath itself is probably pipelined, but normally this is not visible to the programmer.
For each microoperation the datapath is to perform, the control needs to configure the datapath to perform that microoperation. This includes setting datapath signals to the required values to route source operands to where they need to go, get the result to the destination, and, for operations that use the function unit, set it to perform the needed operation.

10. Control Word Group of signals that control the processor
These signals are controller outputs
Some of them are datapath inputs
Tells datapath:
Where to get data
What operation to perform on the data
Where to put result
Includes:
Register addresses, mux selects, enables…
So, how does the datapath get the information it needs to accomplish a particular microoperation? The control unit generates the control word based on the instruction being executed. Most of the control word signals are inputs to the datapath. These signals control the multiplexers and address inputs that direct the data through the datapath, the operation of the function unit, the write enables for the register file and memory, and control other structures within the processor. We’ll look more closely at how this works for our example processor when it needs to execute different types of operations.

11. To Perform ALU Operations…
Data inputs:
A address
MB select
B address or constant value
Operation (FS)
Destination register address (D address)
Register write enable (write) set to 1
MD set to 0
Memory write enable (MW) set to 0
If we need our example processor to perform an ALU operation, we need to specify the control signals that choose the inputs to the function unit, which include the A address, the B mux select and, depending on the selected value, either the B address or the constant. We also must specify the code for the desired ALU operation and the destination register’s address. The register file write signal must be asserted to actually write the result into the register file, and MD must be 0 so that the register file receives the output of the ALU. Finally, since the destination is not in memory, we must set the memory write signal to 0 or we will corrupt information in memory. However, that signal is not shown on this diagram.

12. To Perform A Memory Read…
Memory Address on Bus A
From register file A data output
Data returned on “Data In” bus
MD set to 1
Destination register address (D address)
Register write enable (write) must be 1
Memory write enable (MW) must be 0
When the datapath performs a memory read operation, the memory address is driven out on the A port of the register file. The data is returned from memory on the Data in bus, so MD must be set to 1 to direct that value to the register file. The destination register address must be specified, and the register file write signal must be set to 1. The memory write signal must be 0, since we are reading from, not writing to memory. Note that the register file B address and the ALU’s FS input are don’t-cares, since their values cannot affect the operation.

13. To Perform A Memory Write…
Memory Address on Bus A
From register file A data output
Data to be written on Bus B
MB Select
B address or constant
Memory write enable (MW) must be 1
Register write enable (write) must be 0
When the datapath is performing a memory write operation, the memory address is driven out on the A port of the register file. The data to be written is determined by MB and either the constant input or the B output of the register file. The memory write enable must, of course, be 1 to write to memory, and the register write enable must be 0. All other datapath inputs are don’t-cares.

14. Keep in mind…
Even if certain control signal values are irrelevant for a given operation, some value must still be provided to the datapath
Signals should always have a valid value
Just doesn’t matter whether they are 1 or 0
Write enables should never be “don’t-care”…
These examples are for this specific datapath…
A different datapath may have different control signals in the control word!
A different datapath may have active-low write enables!
Need to look at the datapath, look at the connections, look at the muxes, read the specification…
When we say a signal is a don’t-care, remember that means it still must be a valid 1 or 0, we just don’t care which it is. The write enable signals are NEVER don’t-cares – we ALWAYS care if we are overwriting a value in the register file or memory. Of course, we are looking a single example of a datapath. Other datapaths will have similarities in concept, but you’ll need to look at each new datapath in detail to understand its particular control signals and how they make it work.

15. Using the Datapath Making the datapath do what you need
Figuring out what control signal values you need to give it for a required operation
Figuring out how the datapath responds to a set of control signals
Looking at how the control signals affect multiplexers, write enables, where source information comes from
Examples…
So let’s look at how the example datapath is controlled. We’ll look at this from two perspectives. First, given an operation to perform, how do you configure a given datapath to perform that operation? Second, what operation will a given datapath perform for a given set of input values? We’ll look at a few examples of each.

16. R5  R0 AND R1 1 5 1 X
11002
MW = 0
To perform the operation R5 gets R0 AND R1, we know that the function unit needs to do an AND, so FS must be We select the operands R0 and R1 from the register file. We configure mux B to use the B data output of the register file, which also means that the unused mux data input is a don’t-care. We need to store the ALU output to register R5, so we configure mux D, set the destination address to 5, and assert the register file write enable. Finally, the memory write signal must be set to 0. Now the datapath performs R5 gets R0 AND R1.

17. R2  rotr R2 1 2 X 2 X
10112
MW = 0
To perform the operation R2 gets R2 rotated right, we know that the function unit needs to do a rotate right, so FS must be The ALU uses its B input for rotates, so we select R2 on the B port and the A port is a don’t-care. We configure mux B to use the value from the register file, so its other data input is a don’t-care. We need to store the ALU output in register R2, so we configure mux D, set the destination address to 2, and assert the register file write enable. Finally, the memory write signal must be set to 0. Now that same datapath performs R2 gets R2 rotated right.

18. R7  mem[R0] 1 7 X X X
XXXX2
MW = 0
Next we want to read from memory at the address contained in register R0. The memory address needs to appear on Bus A, so we set the register file A address to 0. We are receiving data from memory, not providing data to it, so the data output to memory is not used and all signals related to Bus B are don’t-cares. We route the data returned from memory to the register file, set the destination to R7, and assert the register file write enable. The function unit isn’t used so FS is a don’t-care. Finally, the memory write signal must be set to 0. Now the datapath will read from memory at the address contained in R0 and store the data returned from memory into R7. 1

19. mem[R4]  R6 X 4 6 X
XXXX2
MW = 1
To write the value in register R6 to memory at a location specified by register R4, we need to put the contents of R4 on Bus A, which provides the memory address. Bus B provides the data for a memory write, so we need to direct the value in R6 to Bus B. We are not writing to the register file, so its write enable must be 0. We are, on the other hand, writing to memory, so we set the memory write signal to 1. The remaining datapath signals cannot affect the operation, so they are don’t-cares. Now the datapath writes the value in register R6 to the memory location specified by R4. X

20. What Does It Do? R 4  R1 AND 5 D addr = 100 A addr = 001 B addr = 111
MB = 1
MD = 0
Reg write = 1
Mem write = 0
Constant = 510
FS = 1100 (AND) 4 1 7 5 1
11002
MW = 0
Let’s look at this from the opposite perspective. What will the datapath do in response to these input signal values? To answer that, we first put those values on the corresponding inputs in the block diagram. Then, we trace through the circuit to see what happens. The first question to ask is, what is the destination?
Well, we are not writing to memory, but we are writing to the register file. So our destination is a register. In fact, it is register R4. Next we need to figure out what is producing the value that will be written to this destination. Mux D is selecting the function unit output, so it’s an ALU operation. Since FS=1100, the function unit is doing an AND. So, what are the operands for the AND? The A input to the function unit is coming from R1. The B input to the function unit comes from the B mux, which is choosing the constant value 5. So, the datapath is performing the operation R4 gets R1 AND 5. Notice that the B address did not matter because it could not affect the operation. R 4  R1
AND 5

21. What Does It Do? R 4  mem[ R1 ] D addr = 100 A addr = 001
B addr = 111
MB = 0
MD = 1
Reg write = 1
Mem write = 0
Constant = 510
FS = 1100 4 1 7 5
11002
MW = 0
Now, let’s repeat the analysis with slightly different values. All of the datapath input values are the same as the previous example except for MB and MD. The operation’s destination is again R4, since the register file is write-enabled with a destination address of 4. Mux D is now selecting the value returned from the data memory, so we are performing a memory read. The address for the memory read, which appears on Bus A, is given by register R1. Notice that none of the signals related to Bus B matter for this type of operation, so we did not need to examine their values. R 4 
mem[ R1 ] 1

22. ECE 352 Digital System Fundamentals
Basic Processor Structure
In this video, we’ve shown you the key parts of an example processor and how they work. In the next video, we’ll talk more about the general operation of our example processor and how it executes instructions.