1. C Model Sim (Fixed-Point) -A New Approach to Pipeline FFT Processor
Presenter: Chia-Hsin Chen,
Yen-Chi Lee
Mentor: Chenjo
Instructor: Andy Wu

2. Outline FFT Review FFT on Hardware What’s Fixed-Point Model Analysis
RTL Implementation
Conclusion & Future Works
Reference
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3. FFT Review An efficient algorithm computes DFT Twiddle Factor:
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4. Radix-22 DIF Algorithm Proposed by S. He and M. Torkelson
Applying a 3-dimensional linear index map
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5. Radix-22 DIF Algorithm (cont.)
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6. R22SDF Pipeline FFT
Example: N=256
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7. Floating Point vs Fixed-point
Use many bits to represent a number
More precise but more computationally demanding
Fixed-point
Use finite bits to represent a number
For hardware implementation
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8. Fixed-Point Model Quantization Saturation Truncation
input & twiddle factor
Saturation
BF2I & BF2II
Truncation
multiplication
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9. Fixed-Point Model (Cont.)
Quantization
For initial values (input & twiddle factor)
Table look up techniques
Saturation
For addition
If there is a carry-out from MSB, set the number to maximum
Truncation
For multiplication
Store the required bits form MSB, and omit the rest
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10. C/C++ Simulation
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11. Signal-of-Quantization-Noise Ratio
SQNR : ratio of signal power to noise power
Error range lies in ±1/2 LSB
For each additional bit, the SQNR goes up by about 6dB
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Owen, Lee

12. Requirements 64-point R22SDF Dynamic range for input data:[-4,4]
Number of bits for input data:10~14
Number of bits for output data:16~20
SQNR≧50dB
Evaluation Equation:
Score = Area * (clock period)2
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13. Analysis Overview Worst case for integer part :
input x[n]=4 for n=0~63
→ maximum output X[0]=4*64=256
→ needs 8 bits for integer part
But it is not often the case
Based on the simulation result, 7 bits is enough
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Owen, Lee

14. Analysis Overview(Cont.)
Fractional part and twiddle factor are closely related
Fix one of them and alter the other, the effect is not obvious
Therefore, fractional part and twiddle factor have to be increased simultaneously
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15. Plotting (Fix Integer Part)
Fix integer part(5 – 8 bits)
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16. Average Case vs Single Case
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17. Plotting (Fix Fractional Part)
Fix fractional part(7 – 10bits)
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18. Plotting (Fix Twiddle Factor)
Fix twiddle factor(8 – 11bits)
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19. Average SQNR Table (7-bit integer part)
frac\twi 6 7 8 9 10 11 12 13 5
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20. Possible Sets
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21. RTL Realization Just for functional work
Word-lengths are the same through the whole process
Integer : 8 bits (including sign bit)
Fractional : 8 bits
Twiddle : 12 bits (including sign bit)
Omit area and timing consideration
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22. RTL Realization (Cont.)
16 points
64 points
Logic elements: 2990
Registers : 2054
fmax : 21.46MHz
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23. RTL Realization (Cont.)
Memory storage reducing
Symmetry of twiddle factor
Area reducing
Different word-lengths of adder and multiplier
Power saving
Treat delay block as RAM
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24. Conclusion & Future Works
We find some possible sets that meet the requirement
Apply these sets of wordlengths to our RTL model
Take area & clock period into consideration
Power, if possible
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25. References
S. He and M. Torkelson. “A new approach to pipeline FFT processor.” IEEE Proceedings of IPPS ’96.
S. He and M. Torkelson. “Designing Pipeline FFT Processor for OFDM (de)Modulation.” ISSSE, pp , Sept
J. Y. Oh and M. S. Lim. “New Radix-2 to the 4th Power Pipeline FFT Processor.” IEICE Trans. Electron., Vol.E88-C, No.8 Aug. 2005
E. E. Swartzlander, W. K. W. Young, and S. J. Joseph. “A radix 4 delay commutator for fast Fourier transform processor implementation.” IEEE J. Solid-State Circuits, SC-19(5): , Oct
C. D. Thompson. “Fourier transform in VLSI.” IEEE Trans. Comput., C-32(11): , Nov.1983.
Y. Jung, Y. Tak, J. Kim, J. Park, D. Kim, and H. Park. “Efficient FFT Algorithm for OFDM Modulation.” Proceedings of IEEE Region 10 International Conference on Electrical and Electronic Technology. Vol.2 pp , 2001.
A. M. Despain. “Very Fast Fourier Transform Algorithms Hardware for Implementation.” IEEE Trans. on Computers, Vol. c-28, No. 5, May 1979
A. –Y. Wu. “CORDIC.” Slides of Advanced VLSI
Y. H. Hu. “CORDIC-based VLSI architectures for digital signal processing.” IEEE Signal Processing Magazine. Pp July 1992
J. G. Proakis. D. G. Manolakis. “Digital signal processing” 3rd edition, Prentice Hall
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26. Thanks for Your Attention
Q & A ?
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