1. 1) Latched, initial state Q =1
NAND Gate Based Latch Transitions
A B (AB)’ S R
Clk Q 1 A 1 1 1 B
1) Latched, initial state Q =1 S R
Clk Q 1
0->1 A B
2) Latched to transparent, Clk:0->1, no change in Q, neither S nor R are asserted

2. 4a) Transparent, R:1->0, B:0->1, no change in Q
NAND Gate Based Latch Transitions
A B (AB)’ S R
Clk Q 1
0->1
1->0 A B
3) Transparent, reset is asserted, R: 0->1, B:1->0, Q’:0->1,Q:1->0, Q Flips to 0 S R
Clk Q 1
0->1
1->0 A B
4a) Transparent, R:1->0, B:0->1, no change in Q

3. 5) Latched, R: 1->0, no change in Q
NAND Gate Based Latch Transitions
A B (AB)’ S R
Clk Q 1
0->1
1->0 A B
4b) Starting from 3), transparent to latched, CLK: 1->0, B:0->1, no change In Q S R
Clk Q 1
1->0 A B
5) Latched, R: 1->0, no change in Q

4. 6) Latched, S:0->1, no Change In Q
NAND Gate Based Latch Transitions
A B (AB)’ S R
Clk Q
0->1 1 A B
6) Latched, S:0->1, no Change In Q S R
Clk Q 1
1->0
0->1 A B
7) Latched to transparent, Clk:0->1, A:1->0, Q:0->1, Q’:1->0, Q Sets to 1

5. 8) Transparent to latched, CLK: 1->0, A:0->1, no change in Q
NAND Gate Based Latch Transitions
A B (AB)’ S R
Clk Q 1
0->1
1->0 A B
8) Transparent to latched, CLK: 1->0, A:0->1, no change in Q

6. Rising Edge Triggered D Flip-Flop Transitions
A B (AB)’ D
Clock P4 P3 P1 P2 5 6 1 2 3 Q 4 1 1
TRANSPARENT CLK=0 Holds P1=1 1 1 1
LATCHED 1 1 1
TRANSPARENT CLK=0 Holds P2=1 1 1
1) Initial state, latched, Q=0

7. 2) Rising clock edge, Clk: 0->1, loads the value on D so Q=1=D
Rising Edge Triggered D Flip-Flop Transitions
A B (AB)’ D
Clock P4 P3 P1 P2 5 6 1 2 3 Q 4 1
1->0 1
1->0
0->1
0->1
1->0
0->1
0->1
1->0
0->1 1
1->0 1 1
2) Rising clock edge, Clk: 0->1, loads the value on D so Q=1=D

8. Rising Edge Triggered D Flip-Flop Transitions
A B (AB)’
0->1 D
Clock P4 P3 P1 P2 5 6 1 2 3 Q 4 1 1 1 1 1 1 1 1
0->1 1
0->1
1->0
3) D changes, doesn’t change Q, Q only changes on the rising edge of Clk

9. 4) Clk goes low, Q doesn’t change and is latched
Rising Edge Triggered D Flip-Flop Transitions
A B (AB)’ 1 D
Clock P4 P3 P1 P2 5 6 1 2 3 Q 4
1->0
0->1
1->0
0->1
1->0 1
1->0 1
0->1
1->0 1 1 1 1
4) Clk goes low, Q doesn’t change and is latched

10. 5) No signal changes Flip-flop is loaded with Q = 1
Rising Edge Triggered D Flip-Flop Transitions
A B (AB)’ 1 D
Clock P4 P3 P1 P2 5 6 1 2 3 Q 4 1 1 1 1 1 1 1 1 1
5) No signal changes Flip-flop is loaded with Q = 1