1. Signal processing for High Granularity Calorimeter
The CALORIC chip
Signal processing for High Granularity Calorimeter
Journées VLSI-PCB-FPGA-IAOCAO de l’IN2P

2. International Linear Collider
ILC "could be the next big adventure in particle physics" [
The possible discoveries scientists could make with the ILC [
(Credit: Greg Stewart, SLAC)
ILC BEAM STRUCTURE:
about 300ns between collisions
duration of train of collisions: 1ms
no beam during 199 ms
with 1ms to convert signals and output data  99% of the time with no activity for electronics on detectors
ILC BEAM STRUCTURE
4/7/2019

3. Challenges for next generation of Ecal
Sandwich structure of: thin wafers of silicon diodes & tungsten layers
Embedded Very Front End (VFE) electronics
Deeply integrated electronics
High granularity : diode pad size of 5x5 mm2
High segmentation : ~30 layers
Large dynamic range of the input signal
Minimal cooling available and ~ channels
ILC Calorimeters
« Tracker electronics with
calorimetric performance »
4/7/2019

4. Readout Electronics for High Granularity Ecal
Electrical specifications of the readout electronics:
Dynamic range of the signal delivered by a Si-diode : from MIP (4 fC) to 2500 MIPs (10 pC)
Level of noise limited to 1/10 MIP  SNR ≥ 10
Error of Linearity:
< 0.1 % up to 10 % of the dynamic range (1 pC)
< 1% from 10 % and 100 % of the dynamic range (10 pC)
Power budget limited to 25µW per channel
Power Pulsing required to save power
Analog electronics busy
A/D conv.
DAQ
IDLE MODE
1ms (.5%)
.5ms (.25%)
.5ms (.25%)
198ms (99%)
Axes of MicRhAu:
Synchronous (with beam) analog signal processing: RAZ CSA, shaping with Gated Integrators, latched comparators
Fully differential architecture, except for the Charge Sensitive Amplifier (CSA)
One low-power ADC attached to each channel
Use of a pure CMOS technology, no bipolar transistors 4

5. First prototype channel
Global Linearity better than 0.1 % (10 bits) up to 9.5 pC (2375 MIP).
ENC = 1.8 fC (0.5 MIP) with a single gain stage
Power consumption with power pulsing estimated to 25µW (no digital part)
Results published in IEEE real Time 5

6. Some building blocks
CSA
Ampli. G.I.

7. The CALOrimetry Readout Integrated Circuit
Low noise CSA
Low-gain shaper
12-bits cyclic ADC
ADC 4
New chip designed
Technology AMS CMOS 0.35 µm
Architecture of CALORIC based on the previous channel tested, with some improvements:
Reduction of the power consumption of the CSA
Reduction of the noise of the amplifier of the Gated Integrator
Increase of the analog memory depth to 16
Fully power pulsed 7

8. The CALOrimetry Readout Integrated Circuit
Low noise CSA
x16
Low-gain shaper
12-bits cyclic ADC
ADC 4
x16
High-gain shaper
Gain discri.
Threshold
A High-Gain (about x 20) channel added to reach the MIP-to-noise ratio of 10.
Increasing of analog memory depth to 16
A discriminator indicates the dynamic range of the signal  select the signal to be converted 8

9. The CALOrimetry Readout Integrated Circuit
Low noise CSA
x16
Low-gain shaper
12-bits cyclic ADC
ADC 4
x16
High-gain shaper
Gain discri.
High-gain shaper
Trigger discri.
Amplifier x5
Analog part
A Trigger channel added to select events over the MIP
 The trigger signal determinates if the active memory cell is reset or the signal kept into memory 9

10. The CALOrimetry Readout Integrated Circuit
Low noise CSA
x16
Low-gain shaper
12-bits cyclic ADC
ADC 4
x16
High-gain shaper
Digital Block
(State Machine)
Gain discri. 12
Output
data
High-gain shaper
Trigger discri.
Amplifier x5
Analog part
A digital block controls the chip
Thresholds
Control of the channel 10

11. The CALOrimetry Readout Integrated Circuit

12. Time conversion < 1 ms
Global State Machine
At the end of idle time, digital state machine wakes up and is ready to manage new events.
IDLE
Analog signal
processing
WAIT for 198 ms
No power
1 ms max.
Up to 16 events stored
Time conversion < 1 ms
A/D conversion
x events stored
End of the beam train
DAQ
(not implemented)
All events converted
Bunch Crossing
Wake Up
Master clock of 20 MHz
Analog electronics busy
A/D conv.
DAQ
IDLE MODE
1ms (.5%)
.5ms (.25%)
.5ms (.25%)
198ms (99%) 12

13. Layout of CALORIC Channel area in AMS 350nm : 1.2 mm²
CSA, trigger channel and comparators
Gated Integrator and the 32 memory cells
The cyclic ADC
The digital block
Channel area in AMS 350nm : 1.2 mm² 13

14. Performance of Caloric (1)
Technology AMS 0.35m CMOS
Area 1.2mm2
Supply Voltage 3.3V
Estimated cons. with ILC duty cycle 45 W per channel
ENC (rms value) with CD=30 pF 0.6 fC (3750 e-)
MIP-to-noise ratio 6
Integral Non-Linearity < 0.2% up to 0.4 pC
of the high and low gain channels < 1% from 1 pC to 6 pC
Gain dispersion 1.5% for the low-gain
of the 16 memory cells (rms value) and 2.5% for the high-gain
Trigger channel non-functional  dominated by noise (clock signals)

15. Bug on power pulsing X

16. Power consumption
Evaluation using power pulsing with the ILC duty cycle:
 45 µW/channel
CSA
Trigger channel
High Gain channel
Low Gain channel 16

17. Conclusion Circuit Caloric:
Des fonctionnalités opérationnelles: amplification, filtrage synchrone, mémorisation, numérisation, séquencement
Un bug !!  power pulsing
Difficultés pour atteindre l’objectif de consommation de 25uW en respectant les sensibilité et linéarité requises
Difficultés de détection de très faible charge (0.4fC) en milieu mixte
Ce développement constitue depuis 10 ans une source de R&D fructueuse:
Nombreuses communications
Prise en main d’une techno. « pure » CMOS
Source de building blocks validés: CSA large dynamique, ampli, comparateur, G.I., ADC,..
Développement d’un circuit complexe mixte
Source « d’inspiration » pour développements actuels et futurs 17