1. EMT 511/3 DIGITAL SYSTEM DESIGN
By:
Dr. Mohd Nazrin Md Isa Block 7, Ground Floor,
School of Microelectronic Engineering, Universiti Malaysia Perlis.
nazrin.unimap.edu.my

2. COURSE Introduction

3. Course Outcomes
CO1: Ability to discover and apply computer-aided design tools for design of complex digital logic circuits.
CO2: Ability to design, analyze, synthesize and evaluate complex digital circuits.
CO3: Ability to apply and design with programmable logic.

4. Specific Outcomes After completing this course, you will be able to:
Understand ALTERA FPGA design flow
Identify basic design guidelines for a successful chip design
Differentiate a synthesizable and non- synthesizable HDL designs
Select a proper HDL coding style for fast, efficient digital circuits

5. Delivery and Assessments
Assignment 1 (20%):
(a)Latch Inference and effects (Individual)
Incomplete if-else statement
Incomplete case statement
Incomplete sensitivity list elements
(b) Blocking vs non-blocking signal assignment
Assignment 2 (20%): Modular HDL design (Individual)
Temperature monitoring and controlling system using FPGA Results: resource utilizations, logic levels, critical path, operating frequency.
Design Project (20%): Pipelined Multiplier using SA (group of 2).
Report format: One 4-page IEEE paper
Results (as above)
In-class Exercises/ Discussions
1 : Switches and LEDs
RTL coding
Test bench writing
Behavioral Simulation
2: Binary to Hex Decoder
RTL coding with bugs
HDL debugging
3: Boiler Control System
4: Traffic light controller
5: Multiplier

6. Text books

7. ACADEMIC CALENDAR (PART 1)

8. Introduction

9. Contents Introduction FPGA Design Flow HDL Design For Synthesis
Review of Verilog modeling structure
Review of Verilog data types
Review of Verilog operators
Review of behavioral modeling
Coding for performance tips and tricks
Review of Test bench

10. C/C++ vs HDL

11. C/C++ vs HDL (cont’d)

12. VHDL vs Verilog

13. FPGA Design Flow

14. BASIC FPGA DESIGN FLOW
Andgate.v
Andgate_tb.v
Andgate.sof

15. DE2-115 Board Information

16. DE2-115 Board Information (cont’d)

17. Labs: slide switches, push buttons, Seven Segment displays
The DE2-115 Block Diagram
Labs: slide switches, push buttons, Seven Segment displays

18. Quartus II

19. HDL Synthesis

20. Pin Planner

21. Simulation (using ALTERA Modelsim)
Requires a test bench file (another Verilog module)

22. Configuring bit stream (.sof) FPGA in JTAG Mode
Ensure that power is applied to the DE2-115 board
Configure the JTAG programming circuit by setting the RUN/PROG slide switch (SW19) to the RUN position
Connect the supplied USB cable to the USB Blaster port on the DE2-115 board
The FPGA can now be programmed by using the Quartus II Programmer to select a configuration bit stream file with the .sof filename extension
SOF = SRAM Object File

23. Configuring bit stream (.pof) FPGA in AS Mode

24. HDL Design for Synthesis

25. Importance of HDL
Designs can be described at very abstract level using HDL
can write without sticking to any technology
Functional verification can be done early in the design cycle
can optimize & modify RTL description until meet desired functionality
Tools: E.g:VCS (Verilog Compiled Simulator), Modelsim
HDL design is analogous to computer programming
provide concise representation of design compared to schematic

26. Simulation At Different Levels
RTL
Design represented by Verilog/VHDL RTL code
High simulation performance
Primary method to debug functional problems
Gate
Design represented as a netlist
Netlist generated by implementation tools (synthesis, P&R)
Slow simulation speed
Circuit
Design represented as SPICE netlist
Highest level of accuracy but slowest simulation speed
Used mainly for critical paths, analog circuits and cell characterization

27. Levels of Abstraction

28. Verilog Modeling Structure

29. Modules – What’s Inside?
module name
port list, port declaration (if port presents)
parameters (optional)
declaration of wires, regs & other variables
data flow statements (assign)
instantiation of lower modules
always & initial blocks
all behavioral statements in these blocks
tasks & functions
endmodule statement

30. How to describe the terminals with more than 1-bit?
Modules - Format
module <module_name> (<module_terminal_list>)
<direction_of_terminals> …
<module_internals>
endmodule
E.g. For a D flip-flop, named DFF, with data, clock as 1-bit inputs, & q as output terminal, the module will be defined as:
module DFF (data, clock, q);
input data, clock;
output q; …
<the function of D flip-flop>
endmodule
How to describe the terminals with more than 1-bit?

31. Hierarchical/Modular Design Example
Test_Tb.v
Test bench
Top.v
Top Most
Design Unit
A.v
B.V
Sub-Blocks (cells)
A B C
C.v
Each unit is coded in a separate HDL file (separate HDL module)

32. Hierarchical/Modular Design
Decoder.v
Top Most
Design Unit
KeyIN.v
Sub-Blocks (cells)
A B
SevenSegmenDec.v
Each unit is coded in a separate HDL file (separate HDL module)

33. Modular Design

34. HDL Code

35. Module Instances - Format
Instantiation template:
<original_module_name> <name_of_instance> (<instance_internal_port_list>);
In another module named DFF2, we want to use the DFF module. So, we should write:
Example
module DFF (data, clock, q);
input data, clock;
output q; …
<the function of D flip-flop>
endmodule
module DFF2 (d, clk, q);
input [1:0] d;
output [1:0] q; …
DFF dff1 (d[0], clk, q[0]);
DFF dff2 (d[1], clk, q[1]);
endmodule
instances

36. Module Instances - Purpose
Nested module instances support top-down design hierarchy
Example:
Verilog code (top-down approach) of full_adder
module full_adder (sum, c_out, a, b, c_in)
input a, b, c_in;
output sum, c_out;
half_adder HA1 (w1, w2, a, b);
half_adder HA2 (sum, w3, c_in, w1);
or (c_out, w2, w3);
endmodule
top-down approach
nested module instances

37. Top-down Design & Nested Modules
Exercise:
Based on full_adder code in previous slide, label the following design blocks:
Given:
full_adder
half_adder a
sum b
c_out
module half_adder (sum, c_out, a, b)
HA2
half_adder
HA1
half_adder +

38. Verilog Primitives
Verilog has a set of 26 predefined functional models of common combinational logic gates called primitives
Most basic functional objects
Names are reserved words in Verilog
n-input
n–output, 3-state
and
buf
nand
not or
bufif0
nor
bufif1
xor
notif0
xnor
notif1

39. Verilog Language Rules
Identifiers
Identifiers (name) in Verilog is composed of space-free sequence of upper- and lowercase letters from the alphabet, the digits (0-9), the underscore and the $ symbol
Verilog is case sensitive language
Example:
and2
counter3_updn

40. Verilog Language Rules
White Space
Used to format text of a model
However, might not separate contiguous characters of identifier or keyword, or digits of number

41. Verilog Language Rules
Statement Termination
Text of Verilog model is placed between module and endmodule
Statements in Verilog is terminated by a semicolon (;)
These statements includes:
data types of signals
other elements that describe structural details of a model
executable procedural statements used by simulator to determine the value of signal

42. Verilog Language Rules
Comments
Many designers always neglect to put comments in the code
Comments is an important form of documentation on the functionality/objective of the code
It helps in making the code readable
Single line comments begins with the symbol //
Multiple line comments begins with /* and ends with */

43. Verilog Language Rules (Verilog version 2001)
Example:
module ANDgate (
input A, B,
output reg Y);
(A or B)
begin
Y = A & B; // A and B
end
endmodule
module ANDgate (
Input A, B,
output reg Y);
(A or B)
begin
Y = (A & B)|( A | B); /* (A and B) or
(A or B) */
end
endmodule

44. Verilog Language Rules
Numbers
Numbers in Verilog can be represented as:
Real numbers
Integer numbers
Base numbers (binary,
octal, hex, decimal)
Two types of numbers:
Sized numbers
Unsized numbers
How to write in module:
module ……; ….
integer A, B, C;
A = 4’b0101;
B = 5’o14;
C = 8’ha5;
D = 5’d14;
endmodule

45. Verilog Language Rules
Sized numbers
<size> ‘<base_format> <number>
Decimal value – specifies # bits in the number
Decimal (‘d or ‘D)
Hex (‘h or ‘H)
Binary (‘d or ‘D)
Octal (‘d or ‘D)
Consecutive digits (0, 1, 2, 3, 4 5, 6, 7, 8, 9, a, b, c, d, e, f)
Example:
4’b1111 // 4-bit binary number
12’habc // 12-bit hex number
16’d255 // 16-bit decimal number
DIY:
8’d123 // number?

46. Verilog Language Rules
Unsized numbers
Size?
Have default value of bits (depends to simulator or machine
≥ 32 bit)
‘<base_format> <number>
Decimal (‘d or ‘D)
Hex (‘h or ‘H)
Binary (‘d or ‘D)
Octal (‘d or ‘D)
Consecutive digits (0, 1, 2, 3, 4 5, 6, 7, 8, 9, a, b, c, d, e, f)
Example:
‘hc3 // 32-bit hex number
‘oc3 // 32-bit octal number
765 // 32-bit decimal number
DIY:
’d123 // number?

47. Verilog Language Rules
X or Z values
X : unknown value
Z : high-impedance value
Very important in modeling real circuit
Use the same sized & unsized number format
Example:
12‘h13x // 12-bit hex number, with 4 LSBs unknown
6‘hx // 6-bit unknown hex number
32’bz // 32-bit high-impedance number
6‘hx3 // What is the equivalent number?

48. Verilog Data Types

49. Verilog Data Types

50. ‘wire’ Usage
When using ‘assign’ statement, always use wire declaration
Example:
module ANDgate (A, B, Y);
input A, B;
output Y;
wire Y; // optional
assign Y = A & B;
endmodule
IMPORTANT NOTE!
Any identifier without type declaration has default-type wire
Y is constantly updated with value from A and B

51. Sensitivity list – WHAT IS THIS??
‘reg’ Usage
When using assignment of values in an ‘always’ block or ‘initial’ block, use reg declaration
Example:
module ANDgate (A, B, Y);
input A, B;
output Y;
reg Y;
(A or B)
begin
Y = A & B;
end
endmodule
Sensitivity list – WHAT IS THIS??

52. Verilog Operators

53. Verilog Operators Summary

54. Verilog Operators Summary (cont’d)

55. Concatenation Operator
Single bits of signal can be combined to form a bus or multi-bits signal
The concatenation operator is identified by the symbol “{” and “}”
Example:
QUESTION:
Based on the same module, what is the signal length for:
Input [1:0] A, C;
Input B;
module ………;
input A, B, C,
output [2:0] D;
assign D = {A, B, C};
endmodule
Resulting of a 3-bit signal

56. Logical Operators Logical operators return a single bit result
It is either “1” (true) or “0” (false)
Example (If A = 3, B = 0)
A && B // equals to 0 (logical-1 && logical 0)
A || B // equals to 1 (logical-1 || logical 0)
Operation
Symbol
and
&& or ||
not !

57. Bitwise Operators
Bitwise operators operate on buses and return the result in bus form
Example (if A = 3, B = 0)
A & B // equals to 0 (‘b11 & ‘b00 = ‘b00)
A | B // equals to 3 (‘b11 | ‘b00 = ‘b11)
Operation
Symbol
and
& or |
not ~
xor ^

58. Logical & Bitwise Exercise: What are the result of Y and Z when:
A = 1’b1, B = 1’b0, C = 1’b0 & D = 3’b111
module test1 (A, B, C, D, Y, Z);
input A, B, C;
input [2:0] D;
output [2:0] Y;
output [2:0] Z;
assign Y = D || {A, B, C};
assign Z = D | {A, B, C};
endmodule

59. Conditional Operators
Conditional operators are widely used for conditional checking (? .. :)
Commonly used to model combinational logic
Consist of 3 operands:
input
select/control
output
Conditional operators can be use to represent multiplexer

60. Conditional Operators
module ……; ….
assign Y = control ? inputA : inputB;
endmodule
true / ‘1’
false / ‘0’
output
select/control
inputs
Checks whether ‘control’ equals to 1 or 0
Example:
inA
assign out = sel ? inB : inA ;
out
inB 1
2:1 MUX
sel

61. Shift Operators Two types of shift operator
Shift left for shifting left
Shift right for shifting right
Shift right is identified by symbol “>>”
Shift left identified by symbol “<<”

62. What is the result of Y when
Shift Operation
Example:
What is the result of Y when
inputA = 5’b11010?
module … ; …
assign Y = inputA << 1;
endmodule
Y = 5’b10100
module … ; …
assign Y = inputA >> 2;
endmodule
Y = 5’b00110

63. Equality Operators Two types of equality operator: Logical equal
identified by symbol “==” for equal and “!=” for not equal
results returned are either “0” (false), “1” (true) or “X” (unknown)
Case equal
identified by symbol “===” for equal and “!==” for not equal
always produces results that are “1” (true) or “0” (false)
can identify values of “X” and “Z”

64. Equality Operators Example: module … ; if (inputA == 1’b1)
outputA = 1;
else outputA = 0;
if (inputA != inputB)
outputA = 0;
else outputA = 1;
endmodule
What happen to outputA
when inputA = 0?
outputA =0
when inputA = 0
inputB = 1?
outputA = 0

65. Reduction Operators
Reduction operators function same as logical operators, except that it operates on itself
6 types of reduction operators:
Example ( in = 3’b111 )
out = &in // out = 1 & 1 & 1 = 1
out = ~|in // out = ~(1 | 1 | 1) = 0
operation
and or
xor
nand
nor
xnor
symbol
& | ^
~& ~| ~^

66. Example Exercise: Assume inputA = 4’b1010 module …; …
assign outputA = &inputA; // outputA = 0
assign outputA = |inputA; // outputA = 1
assign outputA = ^inputA; // outputA = 0
assign outputA = ~&inputA; // outputA = 1
assign outputA = ~|inputA; // outputA = 0
assign outputA = ~^inputA; // outputA = 1
endmodule

67. Arithmetic Operators + - * / 4 types of arithmetic operators:
Operation
Symbol
addition +
subtraction -
multiplication *
division /

68. Operator Precedence Verilog evaluates expression left-to-right
Use parentheses when precedence needs to be overridden

69. Behavioural Modeling

70. Contents Definition of Behavioural Modeling Types of Behavioral Models
Continuous Assignments
Single-pass Behaviours
Cyclic Behaviours
Flow Concept in Verilog
Concurrency
Sequential
Constructs for Control Flow in Behaviour Model
‘If-else’ statement
‘Case’ statement

71. Behavioural Modeling There are 3 types of behavioral models:
Continuous assignments (keyword: ‘assign’)
Single-pass behaviours (keyword: ‘initial’)
Cylic behaviours (keyword: ‘always’)

72. Sensitivity List Sensitivity list is associated with an ‘always’ block
Signals that will cause an evaluation of the ‘always’ block MUST be included in the sensitivity list
Example:
module ANDgate (A, B, Y);
input A, B;
output Y;
reg Y;
(A or B)
begin
Y = A & B;
end
endmodule
‘always’ block will be evaluated whenever there is a change in
the signals listed in sensitivity list

73. Behavioural Modeling

74. Activity Flow in Verilog
In Verilog coding, there are two important concept:
concurrency
sequential
Every piece of code that is classed under concurrency is executed at the same time
Every piece of code that is classed under sequential is executed one instruction at a time

75. Concurrent Statements
There can be more than one block of concurrency statements
module ANDgate (A, B, Y, Z);
input A, B;
output Y, Z;
reg Y;
…….
……..
endmodule
Multiple concurrent block (the blocks are executed concurrently)

76. Sequential Statements
A sequential statement is for example a statement that starts with (sensitivity list)”
module seq (A, B, Y);
input A, B;
output Y;
reg Y;
(A or B)
begin
if (A)
Y = 1;
else if ( A != B)
Y = 0;
end
endmodule
Each statement is executed sequentially

77. Concurrency & Sequential
module ANDgate (A, B, Y, Z);
input A, B;
output Y, Z;
reg Y, Z;
(A or B)
begin
Y = A & B;
end
Z = A | B;
endmodule
module test1 (A, B, C, D, Y);
input A, B, C, D;
output [2:0] Y;
wire [2:0] Y;
assign Y[0] = D | A;
assign Y[1] = B & C;
assign Y[2] = ~A ^ (A | C);
endmodule
Which is concurrent, & which is sequential?

78. Activity Flow Control Constructs
These constructs control the activity flow within a behaviour:
Case statements (‘case’)
Conditional statements (‘if-else’)
Loops (‘for’, ‘repeat’, ‘forever’)

79. Conditional ‘if-else’ Statement
Conditional (‘if-else’) statements are sequential statements
Used for multiple conditions
Conditional statement creates logic that depends on priority of the code

80. Conditional ‘if-else’ Statement
(A or B or C)
begin
if (A & B)
Y = 1;
Z = B;
end
else if (A & C)
Y = 0;
Z = 1;
else
Z = 0;
Can you spot the inputs & outputs?

81. Incomplete ‘if-else’ Statement
There 2 conditions:
What happens when a Verilog code with an IF statement but does not have an ELSE but specify all possible combinations
What happens when a Verilog code with an IF statement but does not have an ELSE and does not specify all possible combinations

82. Incomplete ‘if-else’ Statement
Condition 1
‘if’ without ‘else’ but specified all conditions (at the end of the multiple ‘if-else’ statements)
This is the best way of coding because all conditions for the inputs are specified
if (A & B) …;
else if (A & ~B)
else if (~A & B)
else if (~A & ~B)
All possible conditions of inputs A and B are specified

83. Incomplete ‘if-else’ Statement
Condition 2
‘if’ without ‘else’ but only certain conditions are specified (at the end of the multiple if-else statements)
synthesis tool assumes that the previous value of a variable is maintained  LATCH INFERENCE
if (A & B)
Y = 0;
else if (A & ~B)
Y = 1;
What does this code ‘say’:
If A & B is TRUE then Y = 0
If A & ~ B is TRUE then Y = 1
For all other values of A and
B, the previous value of Y is
maintained
NOT all possible inputs for A and B are specified

84. Latch Inference
If a Verilog code is written using IF statement, without all possibilities being specified, a latch is inferred
This is undesirable since it would create unnecessary logic usage (redundant latch)
Solution:
use an ‘else’ statement (for ‘if’ statement) – for default condition
specify all possible conditions for the inputs

85. Alternative for ‘if-else’
Conditional ‘if-else’ statement can be replaced by the usage of continuous assignment (‘assign’)
For the previous Exercise, using ‘assign’ statement:
module boolean (A, B, C, Y);
input A, B, C;
output Y;
wire Y;
assign Y = (~A & B) | (A & ~B & C)
endmodule
WHAT DOES THIS CODE ‘SAY’:
Y=1 (TRUE) when the conditions of A, B and C are fulfilled

86. ‘Case’ Statement
Case statement is used to represent different options that can be chosen by a set of select signals
Its functionality is similar to that of a multiplexer
Incomplete declaration for input combinations will result latch
Solution – use ‘default’ statement for other combinations (good design habit)

87. ‘Case’ Statement module mux4_case (A,B,C,D,Sel,Y); input A,B,C,D;
input [1:0] Sel;
output Y;
reg Y;
(A or B or C or D or Sel)
begin
case (Sel)
0 : Y = A;
1 : Y = B;
2 : Y = C;
3 : Y = D;
default: Y = 1'bx;
endcase
end
endmodule A 1 2 3 B Y C D
Put ‘default’ in case statement – good design habit
Sel[1:0]
Case statement executes the statement associated with 1st match found, & not consider any remaining possibilities.

88. ‘Case’ Statement module mux4_case (A,B,C,D,Sel,Y); input A,B,C,D;
input [1:0] Sel;
output Y;
reg Y;
(A or B or C or D or Sel)
begin
case (Sel)
2’b00 : Y = A;
2’b01 : Y = B;
endcase
end
endmodule A 1 2 3 B Y
Sel[1:0]
If Sel[1:0] = “10” and “11”, Y will maintain its previous value hence latch is inferred

89. Put ‘default’ condition to avoid latch
‘Case’ Statement
module mux4_case (A,B,C,D,Sel,Y);
input A,B,C,D;
input [1:0] Sel;
output Y;
reg Y;
(A or B or C or D or Sel)
begin
case (Sel)
2’b00 : Y = A;
2’b01 : Y = B;
default: Y = 0;
endcase
end
endmodule A 1 2 3 B Y
Sel[1:0]
Put ‘default’ condition to avoid latch

90. Case vs. Conditional ‘if-else’
Case statement represents multiplexing conditions
If-else statement represents conditional encoding
Which one is better to use?
If Statement
Case Statement
Creates priority-encoded logic
Creates balanced logic
Can contain a set of different expressions
Evaluated against a common controlling expression
Use for speed critical paths
Use for complex decoding

91. Case vs. Conditional ‘if-else’
Code example of 4-to-1 mux

92. Complete vs Incomplete case statement

93. Complete vs Incomplete if-else statement

94. Lab 2: Incomplete case statementvs

95. Lab 2 (Effects on Logic Utilization)vs
Which one yours?

96. Single-Pass Behavior (‘initial’)
Keyword: begin .. end
Sequential block
Statements Processed in the order they specified (next statement executes after previous statement completes execution)
Delay & event control Relative to simulation time when previous statement completes execution
Keyword: fork .. join
Parallel block
Statements Executed concurrently
Note: Order of statements controlled by delay & event control specified by each statement
Delay & event control Relative to time when block was entered

97. Cyclic Behaviour (‘always’)
Keyword: always
Cyclic activity flow whereby the procedural statements will be re-execute after the last procedural statement has executed
Re-execution process continues indefinitely until the simulation is terminated
They execute procedural statements to generate values of the variable, manipulate, & store the variables in memory

98. Cyclic Behaviour (‘always’)
The statements in cyclic behaviour can be unconditional or controlled by a sensitivity list
Used to model (& synthesize) level-sensitive & edge-sensitive behaviour
level-sensitive  combinational logic
edge-sensitive  sequential logic
posedge (sensitive to +ve edge of signal)
negedge (sensitive to –ve edge of signal)

99. Cyclic Behaviour (‘always’)
Example: 2-input full adder
module full_adder (sum, c_out, a, b, c_in);
input a, b, c_in;
output sum, c_out;
(a or b or c_in)
begin
sum = a ^ b ^ c_in;
c_out = (a & b) | (b & c_in) | (a & c_in);
end
endmodule
sensitivity list
- level-sensitive
block
statement
QUESTION:
How to synchronize this module to a clock signal? Rewrite the module so that the design is sensitive to positive edge of clock.
ANSWER:
Include clock as input signal, & sensitivity list (posedge clock)

100. Single-Pass vs Cyclic initial begin … imperative statements .. end
Runs when simulation starts
Terminates when control reaches the end (execute once & stop)
Good for providing stimulus for testbench
Not use in synthesis
always
begin
… imperative statements ..
end
Runs when simulation starts
Restarts when control reaches the end (continually loop)
Good for modeling / specifying hardware
Use in synthesis

101. Combination of Single-Pass & Cyclic
module clock_gen (clock);
parameter half_cycle = 50;
parameter max_time = 1000;
output clock;
reg clock;
initial
clock = 0;
always
begin
#half_cycle clock = ~clock;
end
#max_time $finish;
endmodule
NOTE:
Usually used in testbench
unconditional ‘always’ block (without sensitivity list)

102. Procedural Assignments
Statement that assigns value to a register variable (i.e. to data objects of type ‘reg’, ‘integer’, ‘real’, ‘realtime’, ‘time’)
The output only can get value when a procedural statement executes

103. Procedural Assignments
3 types of procedural assignments
Blocking Assignment
Use “=” operator
Non-Blocking Assignment
Use “<=” operator
Procedural Continuous Assignment (PCA)
Use keywords ‘assign … deassign’, ‘force … release’

104. Blocking Assignment The blocking assignments operator is “=”
Blocking assignments must evaluate the right-hand-side (RHS) arguments w/o interruption from any other Verilog statements
The assignment is said to "block" other assignments until the current assignment has completed

105. Blocking Assignment
Execution of blocking assignments can be viewed as a one-step process:
“Evaluate the RHS and update the LHS of the blocking assignment without interruption from any other Verilog statement.”

106. Blocking Assignment
If blocking assignments are not properly ordered, a race condition can occur
When blocking assignments are scheduled to execute in the same time step, the order execution is unknown

107. Blocking Assignments Simulation example always @ (posedge clk) a = b;
b = a;
// 2 concurrent ‘always’ block with blocking statements
either (a = b) or (b = a) will be executed first, depend to the simulator implementation
so, values in register a and b will not be swapped  both of the register (a and b) will get the same value
Simulation example
clk a b 5 10 15 20 25
For this example, which ‘always’ block execute first?

108. Non-blocking Assignment
Non-blocking assignment operator is the same as the less-than-or-equal-to operator ("<=").
A non-blocking assignment must evaluates the RHS expression at the beginning of a time step and schedules the LHS update to take place at the end of the time step

109. Non-blocking Assignment
The non-blocking assignments executes concurrently (in parallel) regardless to the sequence appearance in a block statement
Variables from RHS are sampled, held in memory, & used to update the LHS variable concurrently

110. Non-blocking Assignment
The non-blocking assignment does not block other Verilog statements from being evaluated
Execution of non-blocking assignments can be viewed as a two-step process:
Evaluate the RHS of non-blocking statements at the beginning of the time step
Update the LHS of non-blocking statements at the end of the time step

111. Non-blocking Assignment
REMEMBER!
Non-blocking assignments are only made to register data types and are therefore only permitted inside of procedural blocks, such as initial blocks and always blocks
Non-blocking assignments are not permitted in continuous assignments (‘assign’)

112. Non-blocking Assignments
(posedge clk)
a <= b;
b <= a;
// 2 concurrent ‘always’ block with non- blocking statements
at +ve edge clock, the values of all RHS variables are ‘read’ & the RHS expressions are evaluated & stored in temporary variables
during ‘write’ operation, the values stored in temporary variables are assigned to LHS variables  values are swapped correctly, regardless of the order in which the write operation are performed
Simulation example
clk a b 5 10 15 20 25

113. Coding for Performance

114. Verilog Coding for Performance
When modeling sequential logic, use non-blocking assignments
When modeling latches, use non-blocking assignments
Avoid incomplete if/else statement
Avoid incomplete case statement
Pipeline data path to improve speed
Avoid nested CASE and IF/THEN statements
You should always build a synchronous design
Always practice modular design

115. Pipelining Concept fMAX = n MHz fMAX  2n MHz D Q D Q D Q D Q D Q
two logic levels D Q D Q
one level
one level
fMAX 
2n MHz
Inserting flip-flops into a datapath is called pipelining.
Pipelining increases performance by reducing the number of logic levels (LUTs) between flip-flops.
All Xilinx FPGA device families support pipelining. The basic slice structure is a logic level (six-input LUT) followed by a flip-flop.
Adding a pipeline stage, as shown in this example, will not exactly double fMAX. The flip-flop that is added to the circuit has an input setup time and a clock-to-Q time that make the pipelined circuit run at less than double the original frequency.
You will see a more detailed example of increasing performance by pipelining later in this section. D Q D Q D Q

116. Test bench

117. Testbench - Concept
input
DUT
output
Testbench

118. Verilog Testbench Elements
Testbench modules
No ports
DUT module instantiation
Relationship between testbench & DUT specified through component & type instantiation & structural-type specification
Stimuli
Test values assigned to DUT inputs
Monitoring outputs
Monitored using system tasks (input & output changes)

119. Testbench – What’s Inside?
module Testbench ();
endmodule
// stimuli signal declarations
reg …; // for DUT input
wire …; // for DUT output
// stimuli declarations
initial …
always
begin …;
end
# … $finish;
// DUT instatiation
Module_name DUT_or_other_name (…);
// monitoring of result - optional
initial
$monitor (…);

120. Verilog Simulator DUT DUT DUT Monitoring tools VERILOG SIMULATOR DUT
– Verilog simulator environment
VERILOG SIMULATOR
DUT
- Verilog module to be tested
DUT
Testbench
DUT
DUT
Testbench
– separate Verilog module
stimuli
Stimuli
– test values (one block or more) to test DUT

121. Testbench - Example Style 1 module ANDgate (A, B, Y);
input A, B;
output Y;
reg Y;
(A or B)
begin
Y = A & B;
end
endmodule
module ANDgate_tb ();
reg A, B;
wire Y;
integer i;
initial // single-pass behaviour
begin
for (i=0; i<4; i=i+1)
{A, B} = i;
#10; // holds the value for 10 ns
end
ANDgate DUT (A, B, Y);
endmodule
Style 1
DUT
Writing testbench is not rigid to this style only.. HOW TO WRITE IN OTHER STYLE?
Sample of
Testbench

122. This is what you get..
ModelSim Simulation

123. .. also resulting the same waveform!!
Testbench - Example
module ANDgate_tb ();
reg A, B;
wire Y;
initial
begin
A = 0; B = 0; #10; // A & B = 0 for 10 ns
B = 1; #10; // B = 1 for 10 ns 10ns)
A = 1; B = 0; #10 // A = 1 for 10 ns 20ns)
B = 1; #10 // B = 0 for 10 ns 30ns)
end
ANDgate DUT (A, B, Y);
initial // this block is optional
#100 $finish; // stops the simulation at 100 ns
endmodule
Style 2
.. also resulting the same waveform!!

124. Another testbench that results the same waveform..
module ANDgate_tb ();
reg A, B;
wire Y;
initial // initial block for input A
begin
A = 0; #20; // A = 0 for 20 ns
A = 1; #20; // B = 1 for 20 ns 20 ns)
end
initial // initial block for input B
B = 0; #10; // B = 0 for 10 ns
B = 1; #10; // B = 1 for 10 ns 10 ns)
B = 0; #10; // B = 0 for 10 ns 20 ns)
B = 1; #10; // B = 1 for 10 ns 30 ns)
ANDgate DUT (A, B, Y);
initial // this block is optional
#100 $finish; // stops the simulation at 100 ns
endmodule
Style 3
Another testbench that results the same waveform..

125. Examples

126. Switches & LEDs (EX 1)

127. Test bench (EX 1)

128. Simulation Result (EX 1)

129. Seven Segment Display (EX 2)

130. APPENDIX

131. Push Button – Active LOW
Switch is in the DOWN position (closest to the edge of the board), it provides a LOW logic level to the FPGA
Switch is in the UP position it provides a HIGH logic level.

132. Slide Switches – Active HIGH

133. LEDS (Reds and Greens)

134. Switches & LEDs (EX 1)

135. The seven segment display- Active LOW
Common anode
- low logic level to a segment will light it up
- high logic level turns it off

136. Seven Segment Display (EX 2)
How to display number 8, 1 ???
How to the actual LED segment pin ???

137. Slide Switches (EX 2)
H/W
HDL code
PIN
SW[3]
U2_IN [3]
AD27

138. Seven Segment Display (EX 2)
H/W
HDL code
PIN
HEXOUT[6]
U2_OUT[6]
H22