1. Characterization of Long Wire Data Leakage in Deep Submicron FPGAs
George Provelengios, Chethan Ramesh, Shivukumar B. Patil,
Russell Tessier, Daniel Holcomb
University of Massachusetts Amherst
Ken Eguro
Microsoft Research
Comments:
Presentation notes:
Thank the PC for the introduction and say hello to the audience
Rephrase the title and move onto the next slide
Timing: <20 s

2. Contribution Quantifying FPGA channel wire coupling (new metric)
Recovering FPGA channel wire layout
Identifying channel wires prone to data leakage
Information leakage for channel wires on different FPGAs
Comments:
Presentation notes:
Lately, several research works have been studying the coupling that exists between neighboring long wires in FPGAs
In this work, we mainly focus on potential ways the coupling effect can be used in FPGAs
For example, we show that by using the technique described in Ramesh et al. we can use coupling for <briefly go through bullets 2-4>
However, the metric used in that work was found to be sensitive to factors not related to the actual coupling and thus a new one is needed
I would tone down the discussion regarding leakage based on technology nodes. One of the reviewers had a problem with that angle
Timing: <40 s

3. Accurately quantifying coupling – New metric
Comments:
We will NOT get into the details of the two metrics and how one can derive the equations
We will use the picture and the two following pop up slides, though, to briefly explain why the new metric is better
Timing: <1 m (overall: 2 m)

4. Accurately quantifying coupling – New metric
∆RC = count diff. of logic ‘1’ and ‘0
∆𝑅𝐶= 𝐶 1 − 𝐶 0 𝐶 1
Comments:
We will NOT get into the details of the two metrics and how one can derive the equations
We will use the picture and the two following pop up slides, though, to briefly explain why the new metric is better
Timing: <1 m (overall: 2 m)

5. Accurately quantifying coupling – New metric
∆RC = 2.66e-04
∆RC = 4.05e-04
∆𝑅𝐶= 𝐶 1 − 𝐶 0 𝐶 1
∆𝑅𝐶= 𝐶 1 − 𝐶 0 𝐶 1
∆ 𝑡 = 𝑓 0 − 1 𝑓
= 𝑑 𝑟𝑥↑ 0 − 𝑑 𝑟𝑥↑ 𝑑 𝑟𝑥↓ 0 − 𝑑 𝑟𝑥↓
(proposed metric)
Comments:
Pop up slide
∆RC depends on RO frequencies

6. Accurately quantifying coupling – New metric
∆𝑅𝐶= 𝐶 1 − 𝐶 0 𝐶 1
∆𝑅𝐶= 𝐶 1 − 𝐶 0 𝐶 1
∆t = 𝐷𝑖𝑓𝑓. 𝑖𝑛 𝑟𝑖𝑠𝑖𝑛𝑔 𝑡𝑟𝑎𝑛𝑠𝑖𝑡𝑖𝑜𝑛 𝑑𝑒𝑙𝑎𝑦 𝑏𝑡𝑤 ′0′ 𝑎𝑛𝑑 ′1′ − 𝐷𝑖𝑓𝑓. 𝑖𝑛 𝑓𝑎𝑙𝑙𝑖𝑛𝑔 𝑡𝑟𝑎𝑛𝑠𝑖𝑡𝑖𝑜𝑛 𝑑𝑒𝑙𝑎𝑦 𝑏𝑡𝑤 ′0′ 𝑎𝑛𝑑 ′1′
∆ 𝑡 = 𝑓 0 − 1 𝑓
= 𝑑 𝑟𝑥↑ 0 − 𝑑 𝑟𝑥↑ 𝑑 𝑟𝑥↓ 0 − 𝑑 𝑟𝑥↓
(proposed metric)
Comments:
Pop up slide

7. Accurately quantifying coupling – New metric
∆RC = 2.66e-04
∆t = 3.28ps
∆RC = 4.05e-04
∆t = 3.32ps
∆𝑅𝐶= 𝐶 1 − 𝐶 0 𝐶 1
∆ 𝑡 = 𝑓 0 − 1 𝑓
= 𝑑 𝑟𝑥↑ 0 − 𝑑 𝑟𝑥↑ 𝑑 𝑟𝑥↓ 0 − 𝑑 𝑟𝑥↓
(proposed metric)
Comments:
Pop up slide
∆t captures only the change of the receiver delay

8. Characterizing C4 wires for three different devices
The effect is present in three different technology nodes (60 to 20 nm)
∆t/LAB:
CIV: 47.8 fs
S5GX: 14.0 fs
A10GX: 8.2 fs
Comments:
With no more than 2 sentences say what the graph shows
Mention that for more details they could come and checkout our poster
Timing: <30 s (overall: 4 m)
Measured values of ∆t versus length of C4 wire for Cyclone IV, Stratix V and Arria 10 devices

9. Summary Come checkout my poster!
A new metric for accurately quantifying coupling that exists between long wires
Able to measure delay changes on the order of femtoseconds
Using the proposed metric the channel layout can be inferred
Design isolation techniques for reducing data leakage risk can be devised
Characterizing coupling between different long wires types across three FPGA families:
Cyclone IV (60nm), Stratix V (28nm), and Arria 10 (20nm)
Come checkout my poster!
Comment:
Summarize. Mention that they are welcomed to come and checkout our poster where we could continue our discussion
Timing: <1 m (overall: 5 m)

10. Thank You

11. Backup
Slides

12. Measured receiver frequency for different RO lengths
Comments:
Show how the results prove that the new metric is better
Also, point out that the even delay changes in the order of femtoseconds can be accurately quantified
Timing: <30 s (overall: 2 m and 30 s)
The two cases yield a similar value of ∆t but different values of the prior metric (∆RC)

13. Adjacency map of a C4 channel in a CIV device
Characterizing coupling between wires allows inferring channel layout
Design isolation techniques could be used for protecting sensitive wires from eavesdropping
Comments:
In a few words, guide the audience on how to read the graph and mention that having the channel layout enables techniques for protecting sensitive wires
Timing: <1 m (overall: 3 m and 30 s)
Measured value of ∆t per C4 wire segment for all pairs of wires in C4 channel