1. Speaker: I-Chyn Wey Advisor: An-Yeu Wu Date : 2007/03/07
Under-Graduate Project : Probabilistic-Based Noise-Tolerant VLSI Digital Circuit Design for TS-SoC
Speaker: I-Chyn Wey
Advisor: An-Yeu Wu
Date : 2007/03/07

2. The Silicon Age – A Closer Look

3. The VLSI Design Challenge and Limiter in the Next Decade

4. Motivation
For future SoC：
Ultra-Low-Power
Noise-Tolerant

5. Probabilistic-Based Solution : Markov-Random-Field (MRF) Circuit
MRF has been widely used in pattern recognition & communication.
Its operation does not depend on perfect devices or perfect connections.
Determine the most possible
output state jointly!
State Probability maximization to achieve high noise-tolerance

6. The Logic Mapping and Construction of MRF Logic Gate：NAND Gate as Example
Using Berkeley’s 70nm model under 0.2V VDD, by adding the Gaussian noise with zero mean and the variance of 3.4 mV.

8. (a) CMOS_CLA circuit (b) MRF_CLA circuit
Measured Single-Bit Waveform of The CMOS_CLA & MRF_CLA Under 1Vp_p AWGN Noise：
(a) CMOS_CLA circuit (b) MRF_CLA circuit

9. Eye Diagram Measurement Under 1Vp_p AWGN Noise Interference：
(a) CMOS_CLA circuit (b) MRF_CLA circuit

10. What You Will Learn
Basic concept of Probabilistic-based Information Theory-Markov Random Field (MRF)
Noise-Tolerant Design Concept in Nano-scale VLSI Era
Reinforce What You Learn in VLSI and Logic Design Course
Digital IC Design Flow

11. Expect Results Paper Survey Circuit Simulation Presentation Skills
Noise-Tolerant Relative Papers
MRF Relative Papers
Circuit Simulation
MRF Carry look-ahead adder
Presentation Skills

12. References
[1] J. Chen, J. Mundy, Y. Bai, S.-M. C. Chan, P. Petrica and I. R. Bahar “A Probabilistic Approach to Nano-computing,” IEEE Non-silicon Computer Workshop, San Diego, USA, June 2003
[2] K. Nepal, R. I. Bahar, J. Mundy, W. R. Patterson, and A. Zaslavsky. “Optimizing Noise-immune Nanoscale Circuits Using Principles of Markov Random Fields,” GLSVLSI’06, April 2006
[3] K. Nepal, R. I. Bahar, J. Mundy, W. R. Patterson, and A. Zaslavsky. “MRF Reinforcer: A Probabilistic Element for Space Redundancy in Nanoscale Circuits,” IEEE J. Micro. Vol. 26,  Sept.-Oct. 2006