1. Sequential Logic

2. AB Circuit Need to consider hidden input: A B Last Out Out 1 x1 x
Need to consider hidden input:
x = don’t care : 0/1

3. Logic Styles Combinational circuits Output determined solely by inputs
Can draw solely with left-to-right signal paths

4. Logic Styles Sequential circuits
Output determined by inputs AND previous outputs
Feedback loop

5. AB Circuit
If A = 1 output must be 1 A B O 1

6. AB Circuit
If A = 0 and B = 1 output must be 0 A B O 1

7. AB Circuit
If A = 0 and B = 0 output may be 1 or 0 A B O
0/1?? 1

8. AB Circuit Describe next output Ot+1 in terms of current output Ot A BOt 1

9. SR Circuit Set Reset circuit Q : Output state Q' : Opposite of output
Qt+1 Qt 1
illegal

10. Clocks and Triggers

11. State Elements
State elements Memory to preserve state until next clock tick

12. Clocks Crystal Oscillators
Vibrate at known frequency when current applied
Used to generate clock signal:

13. Clocks
Timing can be
Level-triggered : change can happen when clock high
Edge-triggered : change can happen on edge

14. Logisim Clock Clock alternates between high and low Push to cycle
Or turn it on

15. Level Triggered
Level triggered elements change on high clock

16. D Latch D Latch : Stores single bit of Data Level triggered
D : 1 sets S 1
D : 0 sets R 1 D
Qt+1 1

17. Edge Triggered
Edge triggered change on rising or falling edge

18. D Flip Flop D Flip Flop : Stores single bit of Data Edge triggered D
Qt+1 1

19. Memory Systems

20. Memory's Atom Basic building block of processor memory Registers
Static RAM (SRAM)

21. Registers
Register : Write requires clock and write signal

22. Registers
Register
Array of D Flip Flops
Shared Write Enable bit

23. Register File Register file Hardware for all registers Supports Read
Up to two registers
Write
One register at a time

24. Register Read Four registers Two bits to select
One mux for each read select

25. Register Write Write needs: Register to modify Data to store
Write enable signal

26. RAM
RAM Memory
2 bits wide

27. RAM
Decoder to select active memory address

28. RAM Implemented

29. Memory's Atom DRAM – (Memory sticks) Dynamic RAM Capacitor based
Slower
Smaller/Cheaper

30. Scaling Up 4-MB memory from 8 4-Mbit modules 22 bit address
12 bits to pick 4096 rows of memory
10 bits to pick 1 of 1024 columns from module

31. Counting & Control

32. Counting Binary count 0000 0001 0010 0011 0100 0101 ……
Green Flips every step
When green flips to 0, flip yellow
When yellow flips to 0, flip orange

33. Counter Counter : count ticks in binary
Bit N turning off is clock signal for Bit N+1
Q’ wired to each bit’s D – Inverts each clock tick

34. Timer
Binary clock into decoder = timing signals