1. UCSD ECE 111 Prof. Farinaz Koushanfar Fall 2017
Vivado Tutorial
UCSD ECE 111
Prof. Farinaz Koushanfar
Fall 2017
Some slides are courtesy of Prof. Lin

2. Create Project
Click on Create Project on the pop-up window

3. Create Project On the pop-up window, click Next
Specify the name and location before clicking Next again

4. Create Project
Select RTL Project

5. Create Project
You can add your source file now or add them after created the project
Add your source file (exclude Testbenches) from ModelSim
Remember to keep “Copy sources into project” unchecked so any modification you made in Vivado will be saved in ModelSim as well

6. Create Project
We’re using “ZYNQ-7 ZC702 Evaluation Board” for this class.
Click “Board” and select the board before clicking Next and Finish

7. Add Sources In Project Manager
Right click on “Design Sources” and “Add Sources”

8. Add Sources
On the pop-up window, select “Add or create design sources” and click “Next”

9. Add Sources
Select and Add your source files (not testbenches) from ModelSim
Remember to keep “Copy sources into project” unchecked so any modification you made in Vivado will be saved in ModelSim as well

10. Implementation On Flow Navigator Window, click “Run Implementation”
When Prompted to run Synthesis, click Yes

11. Implementation
On the pop-up window, select 1 for “Number of jobs” and click ok

12. Implementation
After the synthesis is done, select “View Reports”

13. Implementation
You can also see the reports by clicking on the Σ symbol on the top panel

14. Implementation Scroll to the bottom of Project Summary
Click “Post- Implementation” then “Table”
Make sure your Utilizations are within 100% (or the limit specified)
Screenshot the Utilization window for submission

15. Constraint
Constraint files are used to specify I/O port connections and timing constraints
To add constraint files: Add sources > Add of create constraints > Create file > write file name > ok > finish

16. Constraint

17. Constraint

18. Constraint
Start with a conservative clock period and run implementation
Observe the timing report by clicking on “Implemented Timing Report” on Project Summary (click Σ symbol on the top panel)
connect design I/O ports to FPGA I/O pins
timing constraints
clock period in ns
period/2
set_property PACKAGE_PIN Y9 [get_ports clk]
set_property PACKAGE_PIN G19 [get_ports rst]
set_property PACKAGE_PIN E15 [get_ports checksum]
create_clock -period name clk -waveform { } [get_ports clk]

19. Constraint
Update the clock period with (current clock period – Worst Negative Slack)
If Worst Negative Slack is +ve, that means you can try with lower periods
If Worst Negative Slack is -ve, that means you need to increase the period, in this case the above equation will increase the period
Also change the waveform
Make sure the specified timing constraint is met

20. Constraint

21. Constraint
Observe the power consumption and temperature too, too high frequency may lead to too high power consumption