1. TIMING ACROSS CLOCK DOMAINBY
CHETHAN MURTHY

2. SLOW TO FAST CLOCK DOMAINS
The setup and hold checks when a path goes from a slower clock domain to a faster clock domain.
Path from a slower clock to the faster clock
Clock definitions example
create_clock –name CLKM \
-period 20 –waveform {0 10} [get_ports CLKM]
create_clock –name CLKP\
-period 5 –waveform {0 10} [get_ports CLKP]

3. STA is performed first by determining a common base period.
When the clock frequencies are different for the launch flip-flop and the capture flip-flop,
STA is performed first by determining a common base period.
Faster clock is expanded so that a common period is obtained.
Expanding clock ‘CLKP’ to base period of 20.00
(old period was 5.00,added 6 edges)
Slow to fast path is checked by setup and hold
Fig:Setup and hold checks with slow to fast path

4. The launch clock is at 0ns while the capture clock is at 5ns.
Hold checks are related to the setup checks and ensure that the data launched by a clock edge does not interfere with the previous capture.
If a setup multicycle of N cycles is specified, then most likely a hold multicycle of N-1 cycles should also be specified.

5. FAST TO SLOW CLOCK DOMAIN
The data path goes from fast clock domain to slow clock domain.
The default setup and hold checks are shown in fig below when the following clock definitions are used
create_clock –name CLKM
-period 20 –waveform{0 10} [get_ports CLKM]
create_clock –name CLKP\
-period 5 –waveform {0 2.5} [get_ports CLKP]

6. There are four timing checks possible setup1,setup2,setup3,setup4.
Fig: Path from fast clock to slow clock domain
There are four timing checks possible setup1,setup2,setup3,setup4.
The most restrictive one is the setup4 check.
Similar to setup hold check, there are four hold checks possible.
The capture edge at0ns does not capture the data being launched at 0ns.