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Mattan Erez The University of Texas at Austin

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1 Mattan Erez The University of Texas at Austin
EE382N (20): Computer Architecture - Parallelism and Locality Lecture 5 – Parallelism in Hardware Mattan Erez The University of Texas at Austin EE38N(20) Spring Lecture 5 (c) Mattan Erez

2 Outline Principles of parallel execution Pipelining
Parallel HW (multiple ALUs) EE38N(20) Spring Lecture 5 (c) Mattan Erez

3 Parallel Execution Concurrency Communication Synchronization
what are the multiple resources? Communication and storage Synchronization Implicit? Explicit? what is being shared ? What is being partitioned ? EE38N(20) Spring Lecture 5 (c) Mattan Erez

4 Parallelism – Circuits
Circuits operate concurrently (always) Communicate through wires and registers Synchronize by: clock signals (including async) design (wave-pipelined) more? EE38N(20) Spring Lecture 5 (c) Mattan Erez

5 Parallelism – Components
Collections of circuits memories branch predictors cache scheduler … includes ALUs, memory channels, cores but will discuss later. Operate concurrently Communicate by wires, registers, and memory synchronize with clock and signals Often pipelined EE38N(20) Spring Lecture 5 (c) Mattan Erez

6 Reminders This is not a microarchitecture class
We will be discussing microarch. of various stream processors though Details deferred to later in the semester This class is not a replacement for Parallel Computer Architecture class We only superficially cover many details of parallel architectures Focus on parallelism and locality at the same time EE38N(20) Spring Lecture 5 (c) Mattan Erez

7 Outline Cache oblivious algorithms “sub-talk”
Principles of parallel execution Pipelining Parallel HW (multiple ALUs) Analyze by shared resources Analyze by synch/comm mechanisms ILP, DLP, and TLP organizations EE38N(20) Spring Lecture 5 (c) Mattan Erez

8 Simplified view of a processor
dispatch (issue) reg. access execute write-back commit fetch decode sequencer memory hierarchy EE38N(20) Spring Lecture 5 (c) Mattan Erez

9 Simplified view of a pipelined processor
dispatch (issue) reg. access execute write-back commit fetch decode sequencer memory hierarchy EE38N(20) Spring Lecture 5 (c) Mattan Erez

10 Simplified view of a pipelined processor
dispatch (issue) reg. access execute write-back commit fetch decode sequencer 1:add r4, r1, r2 2:add r5, r1, r3 3:add r6, r2, r3 1 F D I R E W C 2 3 EE38N(20) Spring Lecture 5 (c) Mattan Erez

11 Simplified view of a pipelined processor
dispatch (issue) reg. access execute write-back commit fetch decode sequencer 1:add r4, r1, r2 2:add r5, r1, r3 3:add r6, r2, r3 1 F D I R E W C 2 3 EE38N(20) Spring Lecture 5 (c) Mattan Erez

12 Simplified view of a pipelined processor
dispatch (issue) reg. access execute write-back commit fetch decode sequencer 1:add r4, r1, r2 2:add r5, r1, r3 3:add r6, r2, r3 1 F D I R E W C 2 3 EE38N(20) Spring Lecture 5 (c) Mattan Erez

13 Simplified view of a pipelined processor
dispatch (issue) reg. access execute write-back commit fetch decode sequencer 1:add r4, r1, r2 2:add r5, r1, r3 3:add r6, r2, r3 1 F D I R E W C 2 3 What are the parallel resources? EE38N(20) Spring Lecture 5 (c) Mattan Erez

14 Simplified view of a pipelined processor
dispatch (issue) reg. access execute write-back commit fetch decode sequencer 1:add r4, r1, r2 2:add r5, r1, r4 3:add r6, r5, r3 1 F D I R E W C 2 3 EE38N(20) Spring Lecture 5 (c) Mattan Erez

15 Simplified view of a pipelined processor
dispatch (issue) reg. access execute write-back commit fetch decode sequencer 1:add r4, r1, r2 2:add r5, r1, r4 3:add r6, r5, r3 1 F D I R E W C 2 3 EE38N(20) Spring Lecture 5 (c) Mattan Erez

16 Simplified view of a pipelined processor
dispatch (issue) reg. access execute write-back commit fetch decode sequencer 1:add r4, r1, r2 2:add r5, r1, r3 3:add r6, r2, r3 1 F D I R E W C 2 3 Communication and synchronization mechanisms? EE38N(20) Spring Lecture 5 (c) Mattan Erez

17 Simplified view of a pipelined processor
dispatch (issue) reg. access execute write-back commit fetch decode sequencer 1:add r4, r1, r2 2:ld r5, r4 3:add r6, r5, r3 4:add r7, r1, r3 1 F D I R E W C 2 L 3 4 EE38N(20) Spring Lecture 5 (c) Mattan Erez

18 Simplified view of a OOO pipelined processor
dispatch (issue) issue (dispatch) reg. access execute write-back commit fetch decode rename sequencer scheduler 1:add r4, r1, r2 2:ld r5, r4 3:add r6, r5, r3 4:add r7, r1, r3 1 F D I d R E W C 2 L 3 4 Communication and synchronization mechanisms? EE38N(20) Spring Lecture 5 (c) Mattan Erez

19 Pipelining Summary Pipelining is using parallelism to hide latency
Do useful work while waiting for other work to finish Multiple parallel components, not multiple instances of same component Examples: Execution pipeline Memory pipelines Issue multiple requests to memory without waiting for previous requests to complete Software pipelines Overlap different software blocks to hide latency: computation/communication EE38N(20) Spring Lecture 5 (c) Mattan Erez

20 Resources in a parallel processor/system
Execution ALUs Cores/processors Control Sequencers Instructions OOO schedulers State Registers Memories Networks EE38N(20) Spring Lecture 5 (c) Mattan Erez

21 Communication and synchronization
Clock – explicit compiler order Explicit signals (e.g., dependences) Implicit signals (e.g., flush/stall) More for pipelining than multiple ALUs Communication Bypass networks Registers Memory Explicit (over some network) EE38N(20) Spring Lecture 5 (c) Mattan Erez

22 Organizations for ILP (for multiple ALUs)
EE38N(20) Spring Lecture 5 (c) Mattan Erez

23 Superscalar (ILP for multiple ALUs)
sequencer scheduler Synchronization Explicit signals (dependences) Communication Bypass, registers, mem Shared Sequencer, OOO, registers, memories, net, ALUs Partitioned Instructions memory hierarchy How many ALUs? EE38N(20) Spring Lecture 5 (c) Mattan Erez

24 SMT/TLS (ILP for multiple ALUs)
EE38N(20) Spring Lecture 5 (c) Mattan Erez

25 SMT/TLS (ILP for multiple ALUs)
sequencer scheduler sequencer Synchronization Explicit signals (dependences) Communication Bypass, registers, mem Shared OOO, registers, memories, net, ALUs Partitioned Sequencer, Instructions, arch. registers memory hierarchy Why is this ILP? How many threads? EE38N(20) Spring Lecture 5 (c) Mattan Erez

26 VLIW (ILP for multiple ALUs)
EE38N(20) Spring Lecture 5 (c) Mattan Erez

27 VLIW (ILP for multiple ALUs)
sequencer Synchronization Clock+compiler Communication Registers, mem, bypass Shared Sequencer, OOO, registers, memories, net Partitioned Instructions, ALUs memory hierarchy How many ALUs? EE38N(20) Spring Lecture 5 (c) Mattan Erez

28 Explicit Dataflow (ILP for multiple ALUs)
EE38N(20) Spring Lecture 5 (c) Mattan Erez

29 Explicit Dataflow (ILP for multiple ALUs)
sequencer scheduler scheduler scheduler scheduler Synchronization Explicit signals Communication Registers+explicit Shared Sequencer, memories, net Partitioned Instructions, OOO, ALUs memory hierarchy EE38N(20) Spring Lecture 5 (c) Mattan Erez

30 DLP for multiple ALUs From HW – this is SIMD
EE38N(20) Spring Lecture 5 (c) Mattan Erez

31 SIMD (DLP for multiple ALUs)
sequencer Synchronization Clock+compiler Communication Explicit Shared Sequencer, instructions Partitioned Registers, memories, ALUs Sometimes: memories, net Local Mem Local Mem Local Mem Local Mem memory hierarchy EE38N(20) Spring Lecture 5 (c) Mattan Erez

32 Vectors (DLP for multiple ALUs)
sequencer Local Mem Local Mem Local Mem Local Mem memory hierarchy Vectors: memory addresses are part of single-instruction and not part of multiple-data EE38N(20) Spring Lecture 5 (c) Mattan Erez

33 TLP for multiple ALUs EE38N(20) Spring Lecture 5 (c) Mattan Erez

34 MIMD – shared memory (TLP for multiple ALUs)
sequencer sequencer sequencer sequencer scheduler scheduler scheduler scheduler Synchronization Explicit, memory Communication Memory Shared Memories, net Partitioned Sequencer, instructions, OOO, ALUs, registers, some nets memory hierarchy EE38N(20) Spring Lecture 5 (c) Mattan Erez

35 MIMD – distributed memory
sequencer sequencer sequencer sequencer scheduler scheduler scheduler scheduler Synchronization Explicit Communication Shared Net Partitioned Sequencer, instructions, OOO, ALUs, registers, some nets, memories memory hierarchy memory hierarchy memory hierarchy memory hierarchy EE38N(20) Spring Lecture 5 (c) Mattan Erez

36 Summary of communication and synchronization
Style Synchronization Communication Superscalar explicit signals (RS) registers+bypass VLIW clock+compiler registers (bypass?) Dataflow explicit signals registers+explicit SIMD explicit MIMD memory+explicit EE38N(20) Spring Lecture 5 (c) Mattan Erez

37 Summary of sharing in ILP HW
Style Seq Inst OOO Regs Mem ALUs Net Superscalar S P SMT/TLS VLIW N/A Dataflow B EE38N(20) Spring Lecture 5 (c) Mattan Erez

38 Summary of sharing in DLP and TLP
Style Seq Inst OOO Regs Mem ALUs Net Vector S N/A P s B SIMD p MIMD S/P EE38N(20) Spring Lecture 5 (c) Mattan Erez

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