1. Introduction to Verilog, ModelSim, and Xilinx Vivado
UCSD ECE 111
Prof. Farinaz Koushanfar
Fall 2018
ECE 111 Fall 2018

2. Software access Lab location: Warren Lecture Hall, WLH- 2217A
For access code see the announcement at TritonEd
The required SWs are installed in lab computers
The Linux server has the ModelSim.
You can also download both software
The instructions are on the website: ware.html
ECE 111 Fall 2018

3. Overview Verilog: Hardware Description Language ModelSim: Simulator
Designing the circuit
ModelSim: Simulator
Verification and debugging
Vivado: Synthesize the code for Xilinx FPGAs
Generating configuration file
Area, timing and power analysis
Has a built-in simulator, but we prefer ModelSim
ECE 111 Fall 2018

4. Verilog
Hardware Description Language
ECE 111 Fall 2018

5. Overview Structural Models Behavioral Models Syntax Examples
ECE 111 Fall 2018

6. Design Methodology HDL Specification
Structure and Function (Behavior) of a Design
Simulation (ModelSim)
Synthesis (Vivado)
Verification: Design
Behave as Required?
Functional: I/O Behavior
Register-Level (Architectural)
Logic-Level (Gates)
Transistor-Level (Electrical)
Timing: Waveform Behavior
Generation: Map
Specification to Implementation
ECE 111 Fall 2018

7. Verilog vs VHDL The “standard” languages Very similar
Many tools provide front-ends to both
Verilog is “simpler”
Less syntax, fewer constructs
VHDL supports large, complex systems
Better support for modularization
More grungy details
“Hello world” is much bigger in VHDL
We will use Verilog in this course
ECE 111 Fall 2018

8. Verilog Module Corresponds to a circuit component
“Parameter list” is the list of external connections, aka “ports”
Ports are declared “input”, “output” or “inout”
inout ports used on tri-state buses
module full_addr (A, B, Cin, S, Cout);
input A, B, Cin; output S, Cout; assign {Cout, S} = A + B + Cin;
endmodule
i/o ports
Module name
input/output declaration
ECE 111 Fall 2018

9. Structural/Behavioral Model
Structural Verilog
List of components and how they are connected
Just like schematics, but using text
Hard to write, hard to decode
Useful if you don’t have integrated design tools
Behavioral Verilog
Describe what a component does, not how it does it
Synthesized into a circuit that has this behavior
ECE 111 Fall 2018

10. Structural/Behavioral Model
Structural : Composition of gates to form more complex module
module xor_gate (out, a, b);
input a, b;
output out;
wire abar, bbar, t1, t2;
inverter invA (abar, a);
inverter invB (bbar, b);
and_gate and1 (t1, a, bbar);
and_gate and2 (t2, b, abar);
or_gate or1 (out, t1, t2);
endmodule
Instantiation name
Primitive name
ECE 111 Fall 2018

11. Structural/Behavioral Model
Behavioral: Describe output as a function of inputs
module xor_gate (out, a, b);
input a, b;
output out;
assign out = a ^ b;
endmodule
assign keyword: continuous assignment
ECE 111 Fall 2018

12. Structural/Behavioral Model
module full_addr (A, B, Cin, S, Cout);
input A, B, Cin;
output S, Cout;
assign {Cout, S} = A + B + Cin;
endmodule
module adder4 (A, B, Cin, S, Cout);
input [3:0] A, B;
input Cin;
output [3:0] S;
output Cout;
wire C1, C2, C3;
full_addr fa0 (A[0], B[0], Cin, S[0], C1);
full_addr fa1 (A[1], B[1], C1, S[1], C2);
full_addr fa2 (A[2], B[2], C2, S[2], C3);
full_addr fa3 (A[3], B[3], C3, S[3], Cout);
Behavioral model to describe the inner module
Structural model instantiating the inner module to generate a larger module (more on module instantiation follows)
Instantiation name
Submodule name
ECE 111 Fall 2018

13. Initial/Always Blocks
initial block is executed only once when simulation starts
Useful in writing test benches (example in discussion on testbench)
always block is continuously executed
It has a sensitivity list associated with it
module xor_gate (out, a, b);
input a, b;
output reg out;
always (a or b) begin
out = a ^ b;
end
endmodule
begin..end is equivalent to {..} in C
sensitivity list: the code inside the block is executed when value of either a or b changes, supports wild card character (‘*’)
ECE 111 Fall 2018

14. Assign Statement An assign statement is executed continuously
An always block with sensitivity list set to ‘*’ is equivalent to assign
Following two are equivalent
module xor_gate (out, a, b);
input a, b;
output reg out;
always (*) begin
out = a ^ b;
end
endmodule
module xor_gate (out, a, b);
input a, b;
output out;
assign out = a ^ b;
endmodule
ECE 111 Fall 2018

15. Verilog “Variables” wire reg
Variable used simply to connect components together
All the variables (including i/o ports) are by default wire
reg
Variable that saves a value as part of a behavioral description
Is NOT necessarily a register in the circuit
wire is used outside initial/always block and reg is used inside always block
Compare the two versions of the xor_gate module
ECE 111 Fall 2018

16. Signal Values Regular logic values Z value: X value 0 and 1 logic
High impedance (open circuit)
Synthesized by a tri-state buffer
E.g., assign output = (output_enable) ? input : 1'bz
X value
Don’t care (Assigned to either 0 or 1 logic, whichever is more helpful for the optimization process )
Applicable to certain input patters that may never occur
ECE 111 Fall 2018

17. Verilog Data Types and Values
Bits - value on a wire: 0, 1, X(don’t care), Z(undriven)
Vectors of bits
Declaration: wire [3:0] A;
A vector of 4 bits: A[3], A[2], A[1], A[0]
Treated as an unsigned integer value
Concatenating bits/vectors into a vector
B[7:0] = {A[3], A[3], A[3], A[3], A[3:0]};
B[7:0] = {4{A[3]}, A[3:0]};
ECE 111 Fall 2018

18. Numbers Format: N'Bvalue N = number of bits, B = base
N'B is optional but recommended (default is decimal)
Number
# Bits
Base
Decimal Equivalent
Stored
3'b101 3
binary 5
101
'b11
unsized
00…0011
8'b11 8
8'b1010_1011
171
3'd6
decimal 6
110
6'o42
octal 34
100010
8'hAB
hexadecimal 42
00…
Slide derived from slides by Harris & Harris from their book
ECE 111 Fall 2018

19. Verilog Numbers 14: ordinary decimal number
-14: 2’s complement representation
12’b0000_0100_0110: binary number with 12 bits (‘_’ is ignored)
12’h046: hexadecimal number with 12 bits
Verilog values are unsigned by default
e.g., C[4:0] = A[3:0] + B[3:0];
if A = 0110 (6) and B = 1010(-6), then C = not i.e., B is zero-padded, not sign-extended
ECE 111 Fall 2018

20. Manual Sign Extension
module signed_tb; reg [3:0] A, B; reg [4:0] C, D; initial begin A = 6; B = -5; C = A+B; D = {A[3], A} + {B[3], B}; end endmodule
Result: C = 17 (10001b) = 6(00110b) + 11(01011b) D = 1(00001b) = 6(00110b) + (-5)(11011b)
sign extension
ECE 111 Fall 2018

21. Verilog Operators Type Symbol Operation Type Symbol Operation
Arithmetic *
Multiply /
Division +
Add -
Subtract %
Modulus
Unary plus
Unary minus
Logical !
Logical negation
&&
Logical and ||
Logical or
Relational
>
Greater than
<
Less than
>=
Greater than or equal
<=
Less than or equal
Equality == !=
inequality
Reduction ~
Bitwise negation
~&
nand | or ~|
nor ^
xor ^~
xnor ~^
Shift
>>
Right shift
<<
Left shift
Concatenation
{ }
Conditional ?
conditional
ECE 111 Fall 2018

22. Verilog Operators Examples: assign A = X | (Y & ~Z);
use of Boolean operators (~ for bit-wise, ! for logical negation)
assign A = X | (Y & ~Z);
assign B[3:0] = 4'b01XX;
assign C[15:0] = 16'h00ff;
assign #3 {Cout, S[3:0]} = A[3:0] + B[3:0] + Cin;
bits can take on four values (0, 1, X, Z)
variables can be n-bits wide (MSB:LSB)
use of arithmetic operator
multiple assignment (concatenation)
delay of performing computation, only used by simulator, not synthesis
ECE 111 Fall 2018

23. Module Instantiation
module MUX_4_1(O, I0, I1, I2, I3, S); input [7:0] I0, I1, I2, I3; input [1:0] S; output [7:0] O; wire [7:0] W0, W1; MUX MUX_1 (W0, I0, I1, S[0]); MUX MUX_2 (W1, I2, I3, S[0]); MUX MUX_3 (O, W0, W1, S[1]); endmodule
output of a module is wire, NEVER reg
Need to keep the order of i/o ports
Instantiation name
Submodule name
ECE 111 Fall 2018

24. Module Instantiation
module MUX_4_1(O, I0, I1, I2, I3, S); input [7:0] I0, I1, I2, I3; input [1:0] S; output [7:0] O; wire [7:0] W0, W1; MUX MUX_1 (.O(W0), .I0(I0), .I1(I1), .S(S[0])); MUX MUX_2 (.O(W1), .I0(I2), .I1(I3), .S(S[0])); MUX MUX_3 (.O(O), .I0(W0), .I1(W1), .S(S[1])); endmodule
i/o ports referenced by name
ECE 111 Fall 2018

25. More Examples module Compare1 (A, B, Equal, Alarger, Blarger);
input A, B;
output Equal, Alarger, Blarger;
assign Equal = (A & B) | (~A & ~B);
assign Alarger = (A & ~B);
assign Blarger = (~A & B);
endmodule
ECE 111 Fall 2018

26. More Example // Make a 4-bit comparator from 4 x 1-bit comparators
module Compare4(A4, B4, Equal, Alarger, Blarger);
input [3:0] A4, B4;
output Equal, Alarger, Blarger;
wire e0, e1, e2, e3, Al0, Al1, Al2, Al3, B10, Bl1, Bl2, Bl3;
Compare1 cp0(A4[0], B4[0], e0, Al0, Bl0);
Compare1 cp1(A4[1], B4[1], e1, Al1, Bl1);
Compare1 cp2(A4[2], B4[2], e2, Al2, Bl2);
Compare1 cp3(A4[3], B4[3], e3, Al3, Bl3);
assign Equal = (e0 & e1 & e2 & e3);
assign Alarger = (Al3 | (Al2 & e3) |
(Al1 & e3 & e2) |
(Al0 & e3 & e2 & e1));
assign Blarger = (~Alarger & ~Equal);
endmodule
ECE 111 Fall 2018

27. ModelSim Tutorial
Simulator
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28. Steps Create the project Add/create Verilog files Add testbench
Compile and Simulate
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29. Create the Project Open a new project: File > New > Project
Specify a name and a location
Leave the other two options as default
Enter project name here
Selected location
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30. Add/Create Files
Create new file: Either click on “Create New File” or right click > Add to project > New File
Enter a name, Set file type to Verilog
Save the file: File > Save (or ctr-S)
ECE 111 Fall 2018

31. Add/Create Files
Double click on the file or right click > edit to edit the file
Add an existing file: Either click on “Create New File” or right click > Add to project > Existing file, then browse for the file
Similarly, add the necessary testbench(s)
ECE 111 Fall 2018

32. Add Testbench
Testbench is a simulation specific Verilog file that is used to provide input values to the module under test.
In the next two slides we provide a simple Verilog file and corresponding testbench.
Detail on testbench later in the course
ECE 111 Fall 2018

33. Add Testbench
module first_module( input i1, i2, output o1, o2 ); assign o1 = i1&i2; assign o2 = i1|i2; endmodule
ECE 111 Fall 2018

34. Add Testbench contd.. Testbench module does not have any input/output
module first_module_tb; // Inputs reg i1; reg i2; // Outputs wire o1; wire o2; first_module uut ( .i1(i1), .i2(i2), .o1(o1), .o2(o2) );
Testbench module does not have any input/output
The inputs will be changed inside an always/initial block
Instantiate the module under test
contd..
ECE 111 Fall 2018

35. Add Testbench
initial begin i1 = 0; i2 = 0; #100; $display("%d %d %d %d\n", i1, i2, o1, o2); i2 = 1;
Wait, only works in simulation
Display the values, similar format as printf C , only works in simulation
contd..
ECE 111 Fall 2018

36. Add Testbench
i1 = 1; i2 = 0; #100; $display("%d %d %d %d\n", i1, i2, o1, o2); i2 = 1; end endmodule
ECE 111 Fall 2018

37. Compile Select all the files and right click to specify compile order
For simple project we can use Auto Generate to generate the order But for larger project we might need to specify the orders by ourselves
Compile all after you have specified the order
ECE 111 Fall 2018

38. Simulate Simulate > start simulation
Under work > find your testbench file
Click ok
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39. Simulate Open wave tab if it did not pop up automatically
In Objects tab, drag the desired input/output into the wave tab
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40. Simulate Specify time to run and hit the run next to it
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