1. Division and Modulo 15 Q A = Dividend B = Divisor Q = Quotient = A/B
R = Remainder B 9
140 A 9 50 45 5 R
Unsigned, integer division
R = A mod B
Shift-Subtract Algorithm
Dividend shifts left each step
Subtract if B is less than Dividend so far

2. Divider/Modulo (Div/Mod) Component
1001
10001
10000
1110
101
Shift-Subtract algorithm
If Divisor is less that Dividend
Subtract
Assign Quotient bit to 1

3. Hints on Verilog Implementation
Behavioral verilog not Structural verilog
Don’t use assign statements, just always and initial blocks
Multi-bit values will be defined as vectors (A, B, etc.)
Inputs and outputs (A, B, Q, R) are wires by default
Cannot assign values to inputs, should not read values from outputs
Outputs should only be assigned once in a block
Should use registers inside the behavior, not wires
<< is shift left and >> is shift right
You can use a for loop