1. Reconfigurable FPGAs for Space – Present and Future
Rick Padovani
Xilinx, Inc.
MAPLD 2005

2. Abstract
The capability to implement reconfigurable digital systems based on FPGA technology is a reality today. Reconfigurability is defined in a continuum ranging from rapid design development, post-deployment hardware modifications, through to runtime reconfiguration for processing and computing. In addition, designer are increasingly looking to FPGA-based computing as performance improvements of traditional Von Neuman processors begin to level off. These topics are of increasing interest to designers of Space-based systems.
Two emerging technologies, Rad Hard by Design (RHBD), and runtime Partial Reconfiguration (PR) will dramatically increase the efficiency and reduce the cost of using reconfigurable FPGAs in Space Applications. Today’s reconfigurable FPGAs are susceptible to Single-Event Effects (SEEs) which can corrupt the configuration memory and affect the user’s design. Reconfigurable FPGAs can be made virtually immune to SEEs through the use of Triple-Module Redundancy (TMR) and configuration memory scrubbing, although these techniques bring added PCB complexity and reduce the number of available logic cells. Efforts are underway to introduce RHBD FPGAs that will be immune to SEEs. FPGAs employing RHBD configuration memory will not require TMR or configuration memory scrubbing for protection against SEEs and will offer increased reconfigurable capability for field upgrades and runtime Partial Reconfiguration (PR).
Runtime PR offers a means for changing design modules on-the-fly, while the “base” design continues to operate uninterrupted. This allows multiple design modules to time-share the same physical silicon resources, thereby reducing device resource utilization, device count, and power consumption.
Partial Reconfiguration is available today, and will become increasingly important for space-based systems where PCB footprint, mass, and power consumption are of even greater concern. This paper will review the present and future state of commercial process technology, reconfigurable FPGA architecture, FPGAs for Space, and the benefits offered by PR and RHBD.

3. Outline
The current state of commercial process technology and FPGA architecture
Computing and the Future
Reconfiguration use models
Partial Reconfiguration
FPGAs for Space-based applications
Rad Hard by Design Development
Conclusions

4. Moore’s Law Continues Fueling Reprogrammable FPGA Advances
Mature
FPGA Product
Technology
Developing
FPGA Product
Technology
Future
Process Technology
Plan continuation of 2 year Technology node cycle
“Traditional Scaling” is starting to be effected by the fundamental material limits of the planar CMOS process
“Equivalent Scaling” or the assimilation of new materials, structures and functional integration will drive continued scaling
180 nm
150 nm
130 nm
90 nm
65 nm
45 nm
32 nm
22 nm
8 nm

5. Architectural Evolution Reconfigurable FPGAs
Programmable “System in a Package”
Domain-optimized System Logic
System
Logic
FPGA Fabric
Block RAM
Embedded Registers and Multipliers
Clock Management
Multi-standard Programmable IO
Embedded Microprocessor
Multigigabit Transceivers
Embedded DSP-optimized Multiplers
Embedded Ethernet MACs
Device Complexity and Performance
Platform
Logic
FPGA Fabric
Block RAM
Embedded Registers and Multipliers
Clock Management
Multi-standard Programmable IO
Embedded Microprocessor
Multigigabit Transceivers
Block
Logic
FPGA Fabric
Block RAM
Embedded Registers and Multipliers
Clock Management
Multi-standard Programmable IO
Glue
Logic
FPGA Fabric
Block RAM
FPGA Fabric
1985
1992
2000
2002
2004
2005

6. Are Von Neumann processors running out of steam?
Lack of increased clock speed is being addressed by:
Increased cache size
Longer pipelines
Trying to do more per cycle
This approach also nearing its limit
Clock Speed
Compute Density of Processors
Source: UC Berkeley HERC and CPUscorecard.com

7. What’s next for Computing Platforms?
Hyperthreading?
Clusters?
Configurable instruction sets?
Configurable coprocessors?
In general, the need for parallel execution is now
recognized as a requirement, as is the desire for
customizable instruction sets

8. Reconfigurable FPGAs to the rescue
For at least 15 years people have seen the Von Neumann limitations and have argued that FPGAs were the ultimate supercomputer
Better programmability – not stuck with a fixed ALU
Parallel processing – not just hyperthreading but limitless opportunities for parallelism
No wasted cost on features that you don’t need
Some traction over the years, but very limited
Numerous chess-playing machines from Deep Thought to Hydra
Craig Venter used Xilinx chips for the Human Genome project
Other people are using Xilinx chips for Bioinformatics
Cray, SGI and others have been using FPGAs as coprocessors to offload certain operations
Berkeley Emulation Engine is a recent example
Numerous companies represented in the consortium have been extolling the virtues of FPGA computing for a long time

9. Raw Processing Performance Characteristics and Comparisons
Three axes of performance
Computational capability
Memory Bandwidth
IO Bandwidth

10. Why has adoption taken so long?
Traction has been limited by programming model
Direct C translation to gates
Definite progress in development and productization
Limited customer acceptance in the supercomputer market but picture may be changes
Direct HDL design
Difficult to implement current applications of supercomputing in HDL
Need for high connectivity lowers performance
To date, the only model in widespread use for supercomputing-type applications is HDL

11. New use models enabled with Reconfigurable FPGAs
Spectrum of Reconfiguration
Occasionally
Periodic
Frequent
Run-time
Field Upgrades Rapid Design Data Processing Networking Signal Processing
More efficient use of hardware
Adaptive hardware algorithms
Design modules that time share device resources
Reduced device count and lower power consumption

12. FPGA Partial Reconfiguration
Configuration Memory Layer
User Logic Layer
Think of an FPGA as Two Layers
Configuration Memory Layer
User Logic Layer
Configuration memory controls functions on user logic layer
Partial Reconfiguration allows a portion of device to be changed while the rest is still running
Documented in XAPP 290
What FPGA Configuration Memory Controls
All interconnection (wiring)
Logic Definition (Look-up Tables or “LUTs”)
Multiply by, divide by, etc.
Inversion
Feature selection
Interface to hardwired blocks, e.g. PPC
Pipeline on/off
ECC enable/disable
BRAM width
I/O Modes
>really EVERYTHING!

13. Partial Reconfiguration Modules (PRMs)
XC2VP30
PRM_A0
PRM_A1
PRM_A2
PRM_B0
PRM_B1
PRM_B2
PR Region A
PR Region B
One or more PR regions can be defined
Multiple PRMs can be defined for each region

14. Present Rad Tolerant Products Future RadHard by Design Products
Reconfigurable FPGAs for Space Product Development Strategies – Present and Future
Exploit inherent TID hardness of advanced commercial processes
SEL immunity achieved with epitaxial layer on P+ substrate, multiple substrate taps and lower core voltage
SEE hardness will improved with RadHard by Design techniques:
Present Rad Tolerant Products
Future RadHard by Design Products
Configuration
Memory Layer
Effective immunity by utilizing Partial Reconfiguration to “scrub” Configuration Memory
Immunity by RadHard Circuit Design
Eliminates need for scrubbing and configuration manager circuit overhead
User Logic
Layer
Xilinx TMR (XTMR) confers effective SEU and SET immunity
TMR significant
Multiple Embedded Cores, e.g., PPC, use TMR with hardened FPGA fabric
Dramatic increase in available resources and ease of design
Hardwired FPGA
Control Logic
Small cross section SEFIs requires full device reconfiguration
FPGA power cycle is not required
Eliminates SEFIs

15. FPGA Radiation Tolerance TID Trends vs Product/Technology
TID tolerance of Military-grade FPGAs with full production test:
350nm - XQ4000XL
60K Rads (Si)
220nm - XQVR (Virtex)
100K Rads (Si)
150nm - XQR2V (Virtex-II)
200K Rads (Si)
130nm - XQR2VP
250K Rads (Si)
90nm (Preliminary)
300K Rad (Si)
Process trends*:
Gate oxide continues to thin
Oxide tunnel currents increase
Gate stress voltage decreases
*See “CMOS SCALING, DESIGN PRINCIPLES and HARDENING-BY-
DESIGN METHODOLOGIES” by Ron Lacoe, Aerospace Corp
2003 IEEE NSREC Short Course 2003

16. Applied Mitigation TMR + Scrubbing
FPGA can manage its
own configuration scrubbing!
Single FPGA with TMR and Configuration Scrubbing
Continuous, uninterrupted operation (except SEFI)
Can employ readback for error detection
Scrub controller detects and handles SEFIs
Critical data processing applications (Communications, Navigation)
PROM
Scrub
Control
Virtex-II
TMR

17. Xilinx TMR (XTMR)
Single-String
XTMR

18. Logic Capacity of Virtex Rad Tolerant Families Current Virtex Families with TMR Mitigation vs. Future RHBD Families
125
Current Virtex Families
Future RadHard
by Design Families
100 75
Available Logic Cells (K) 50
Partial TMR
Effective Array Utilization Range
for a typical TMR Design 25
Full TMR
XQVR XQR2V XQR2VP SIRF 4V100
(Virtex) (Virtex-II) (Virtex-II pro) (Virtex-4 RHBD)

19. RadHard by Design Program
SEU Immune Reconfigurable FPGA (SIRF)
Phase-I Test Chip
Vehicle to determine and prove hardening strategies for key architectural elements
Test Chip includes a range of design variants for each key element
Radiation Testing in 1Q06
Phase-2 Product Implementation
Optimal RHBD implementation of Virtex-4 architecture
Embedded hard core, e.g., PPC and MGT, hardening strategies evaluated during Phase-1 and current V-IIpro testing
Phase-1: Design Feasibility, Test Chip and Trade Study
Phase-2: SIRF Product Development and Fabrication

20. Conclusions
CMOS scaling will continue well into the next decade fueling reconfigurable FPGA architectural advances and system-level integration
The computing industry is trying to increase performance with parallel execution and reconfigurability today and this is clearly the way of the future
Performance of FPGAs as a compute platform exceed conventional processors in all three performance vectors; implementing an effective programming model is the main issue the industry is working hard to solve
Partial Reconfiguration capability is here today enabling new use models and software support tools are imminent
Rad Tolerant Reconfigurable FPGAs available today achieve virtual SEE immunity by applying Partial Reconfiguration and soft TMR techniques
Rad Hard by Design Reconfigurable FPGAs are under development and will offer a dramatic increase in available logic cells and radiation performance while freeing up reconfiguration resources for more efficient use of hardware, reconfigurable processing or computing applications