1. ANALOG TO DIGITAL
CONVERTER
(ATD)

2. HCS12 CPU Internal Bus SCI 1 SCI 1 ATD 1 ATD 12K SRAM 256K FLASEEPROM
12K
SRAM
256K FLASEEPROM
Internal Bus
SPI 2 or
PWM CH
4-7
SPI 1 or
PWM CH
0-3
SPI 0
BKP INT MMI
PWM 8
CHAN
HCS12 CPU
SIM
CM BDM MEBI
PIM PLL PIT
msCAN 4 or
IIC
msCAN 3
msCAN 2
msCAN 1
BDLC or
msCAN
ECT 8
CHAN 4K
BYTES
EEPROM

3. Analog to Digital Converter
FEATURES:
• 8/10 Bit Resolution.
• 7 usec, 10-Bit Single Conversion Time.
• Sample Buffer Amplifier.
• Programmable Sample Time.
• Left/Right Justified, Signed/Unsigned Result Data.
• External Trigger Control.
• Conversion Completion Interrupt Generation.
• Analog Input Multiplexer for 8 Analog Input Channels.
• Analog/Digital Input Pin Multiplexing.
• 1 to 8 Conversion Sequence Lengths.
• Continuous Conversion Mode.
• Multiple Channel Scans.

4. A/D Register Map

5. A/D Clock Select/ Prescaler
• Maximum A/D Clock = 2.0 MHz (MININUM A/D CLOCK = .5 MHz)
PRS0-PRS4
Divide
By 2
SYSTEM CLOCK
5-Bit Modulus Counter
Prescaler
A/D Clock
ATDCTL4(HI) - A/D CONTROL REGISTER
Address offset
$0004
SRES8 - A/D Resolution Select
1 = Select 8-bit Resolution
0 = Select 10-bit Resolution
SAMPLE TIME SELECT
SMP [1:0]
Sample Time 00
2 A/D Clock Periods 01
4 A/D Clock Periods 10
8 A/D Clock Periods 11
16 A/D Clock Periods
• 5-Bit Modulus Counter Prescaler
- Controlled by PR[4:0] in A/D Control Register 0
- Divides system clock by any integer from 2 to 64, inclusive(PRS value + 1)
- If PRS[4:0] = 0, then prescaler is bypassed
Note: PRS[4:0] must not make A/D Clock > 2 MHz.

6. Conversion Timing A/D Clock Always 2 Clocks 2, 4, 8, 16 Clocks
Conversion time calculation Examples:
(Assume 2MHZ A/D Clock)
Example 1:
Conversion Time = Initial Sample Time + Programmed Sample Time + Resolution Period
= = 14 A/D Clocks
= 7uSec
Example 2:
= = 28 A/D Clocks
= 14uSec

7. A/D Control Registers ETRIGLE - External Trigger Level/Edge Control
ATDCTRL2 - A/D CONTROL REGISTER 2
Address offset
$0002
ASCIE - A/D Sequence Complete Interrupt Enable
1 = Enable A/D Interrupts
0 = Disable A/D interrupts
ADPU - A/D Power-Up Enable/Disable
1 = Apply Power to A/D
0 = Reduce power by disabling A/D
ASCIF - A/D Sequence Complete Interrupt Flag
1 = Sequence complete interrupt
0 = no interrupts pending
AFFC - A/D Fast Conversion Complete Flag Clear
1 = Fast Flag clear sequence
0 = Normal Flag clear sequence
AWAI - A/D Wait Mode
1 = Enable Conversion in CPU Wait
0 = Disable Conversion in CPU Wait
ETRIGLE - External Trigger Level/Edge Control
1 = Level Mode - Active Level Gate
0 = Edge Mode - Active Edge Mode
ETRIGP - External Trigger Polarity Control
1 = Active High Level or Rising Edge Active
0 = Active Low Level or Falling Edge Active
ETRIGE - External Trigger Mode Enable
1 = External Trigger Enabled
0 = External Trigger Disabled

8. A/D Control Registers (Cont’d)
ATDCTRL3 - A/D CONTROL REGISTER 3
Address offset
$0003
FIFO - Result Register FIFO
1 = Result Registers do not Map to Conversion sequence
0 = Result Registers Map to Conversion Sequence
Conversion Sequence Length Coding

9. A/D Control Registers (Cont’d)
ATDCTRL5 - A/D CONTROL REGISTER 5
Address offset
$0005
CHANNEL SELECTION
0 0 0 = Chan 0 -
= Chan 7
DJM - Result Register Data Justification Mode
1 = Right Justified Mode
0 = Left Justified Mode
SCAN - Continuous Conversion Sequence Mode
1 = Select Continuous Conversion Sequence ( 4 or 8 )
0 = Select Single Conversion Sequence
( 4 or 8 times & stop )
DSGN - Signed/Unsigned Result Data Mode
1 = Select Signed Result
0 = Select Unsigned Result
MULT - Multiple Channel Sample Mode
1 = Select Multiple Channel Conversion Mode
0 = Select Single Channel Conversion Mode
Note: A write to this register aborts current
conversion sequence and initiates a new
conversion sequence.

10. Result Registers Left Justified Result Data Address Offset
$ $0011 -
$001E - $001F
Right Justified Result Data
Address Offset
$ $0011 -
$001E - $001F

11. A/D Registers (Con’d) ATDSTAT - A/D STATUS REGISTER
Address Offset
$0006
$0007
SCF - Sequence Complete Flag
- Set at end of conversion sequence in single conversion mode (SCAN = 0)
and at the end of first conversion sequence in continuous conversion mode (SCAN = 1).
- A write to this register clears SCF flag when (AFFC = 0).
ETORF - External Trigger Overrun Flag
-Sets if active edges occur while conversion sequence in progress.
FIFOR - Sets when the Result Register has been written before it was read by the CPU ( CCF was not cleared).
CC[2:0] - Conversion Counter
3-Bit counter that points to the next channel to be converted in 4 or 8 count sequence.
CCF7 -CCF0 - Conversion Complete Flags for individual A/D channels.
- Set upon end-of-conversion for each associated A/D channel.
- Cleared when associated A/D result register is read.

12. A/D Port Register A T D P ATDDIEN - ATD Digital Input Enable
PORTAD1 - A/D PORT Data Register
Address Offset
$000F
ADA7
ADA6
ADA5
ADA4
ADA3
ADA2
ADA1
ADA0 A T D P
ATDDIEN - ATD Digital Input Enable
Note : Any port pin may be used as A/D or as GP Input.