1. Total Development Cost (M$)45 40 35
Design /
Verification
& Layout 30
Total Development Cost (M$) 25 20
Software 15
Figure 1 Caption – Increasing costs are limiting access to 90-nm design development.
Test & Product
Engineering
Masks & Wafers
0.18 µm
0.15 µm
0.13 µm
90 nm
65 nm
45 nm

2. Minimizing Risks of Custom Silicon
Delay ASIC Investment
ASIC
HardCopy II
Fast Path to Production
Low Up-Front Investment
TAT in Weeks
Stratix II
Demonstrate Technology
$0 NRE
Instant TAT
System Volume (Ku)
Initial Investment (M$)
Figure 2 Caption – Utilizing a structured ASIC such as Altera’s HardCopy allows designers to delay costly ASIC commitment, providing low up-front investment and a quicker production ramp.
Time

3. ASSP Startups– A New Approach
HDL
FPGAStart
FPGACust_1
FPGACust_2
FPGACust_3
FPGACust_4
FPGACust_5
FPGASuperset
Figure 3 Caption – An ASSP vendor can integrate customer requests, modifications and enhancements into an FPGA-based design; then, after customer validation, the customer can create a HardCopy structured ASIC from the superset FPGA.
SUPERSET
Customer 5