1. "Computer Design" by Sunggu Lee
Intro. to PLDs
Types of Programmable Logic Devices (PLDs)
Programmable Logic Array (PLA)
Programmable AND-Array Logic (PAL)
Generic Array Logic (GAL)
PAL, Configurable and Erasable (PALCE)
Field Programmable Gate Array (FPGA)
Programmable Read-Only Memory (PROM)
"Computer Design" by Sunggu Lee

2. "Computer Design" by Sunggu Lee
Logical Structure of a PLA
Programmable Connections
Product Terms
Programmable Connections
Sum of Products Expressions
"Computer Design" by Sunggu Lee

3. "Computer Design" by Sunggu Lee
Methods for Programming Connections
Use PLD Programmer (Rom Writer) for Programming
Determines where connections are to be made
"Computer Design" by Sunggu Lee

4. "Computer Design" by Sunggu Lee
Problems with PLAs
Too many programmable connections
Mostly unused
Leads to costly and difficult to manufacture devices
Alternatives to PLAs
Programmable AND-Array Logic (PAL)
Fixed matrix of OR gates of various sizes
Only AND matrix is programmable
Registerd PAL Device
PAL with a set of flip-flops that can be optionally connected
GAL, PALCE
Erasable versions of PALs
Includes several flip-flops for sequential circuit implemention
"Computer Design" by Sunggu Lee

5. "Computer Design" by Sunggu Lee
PROMs and EPROMs can also be used as PLDs
PROM
Used mainly as a memory device
Example: Boot ROM (BIOS) used in PC’s
EPROM
Can be erased by exposure to ultraviolet light
Address lines are connected to inputs (variables)
Data lines are connected to function outputs
Programmed connections are the “contents” of the PROM or EPROM > minterms
Physical construction of PLA devices
Figs. 3.6 and 3.7: NOR-NOR-invert structure
equivalent to invert-AND-OR > WHY?
"Computer Design" by Sunggu Lee

6. "Computer Design" by Sunggu Lee
minterms
Logical Structure of a PROM
canonical SOPs
"Computer Design" by Sunggu Lee

7. "Computer Design" by Sunggu Lee
Example 3.1: Using a 256 x 4 PROM Device,
implement f1 = w’xy’+x’yz’ + xz and f2 = a’b’y + abx’y’ + a’bx’y’
"Computer Design" by Sunggu Lee

8. Example PAL Structure: PAL18L4
"Computer Design" by Sunggu Lee

9. "Computer Design" by Sunggu Lee
Example: Z0 = A’BC + C’D
Z0’ = (A + B’ + C’) (C + D’) = AC + B’C + AD’ + B’D’ + C’D’
"Computer Design" by Sunggu Lee

10. Sequential PAL and GAL Devices
Registered PAL
Includes “registered” outputs (outputs of D flip-flops)
GAL and PALCE Devices
Erasable / reprogrammable versions of registered PALs
Configurable as a combinational or sequential device
Example: GAL16V8R
GAL configured as a “PAL16R8 type” device
8 of the 16 inputs come from the D flip-flop outputs
Question: What are these types of inputs called?
"Computer Design" by Sunggu Lee

11. "Computer Design" by Sunggu Lee
* PAL16R8
Configured as a
3-bit Gray Code
Counter
"Computer Design" by Sunggu Lee

12. Field Programmable Gate Arrays
Most complex type of chip that can be “programmed” to implement arbitrary circuits
Many competing manufacturers
Actel, Altera, Cypress, Lattice, Xilinx, etc.
Competitive Factors
large number of logic gates, high speed, flexibility, low cost, reprogrammability (can be traded off for speed)
FPGA: a programmable array of simpler PLDs
FPGA: field programmable version of “gate array”
"Computer Design" by Sunggu Lee

13. "Computer Design" by Sunggu Lee
Basic Structure of a Gate Array (a “simple ASIC”)
"Computer Design" by Sunggu Lee

14. "Computer Design" by Sunggu Lee
XC4010XL Xilinx FPGA Block Diagram
"Computer Design" by Sunggu Lee

15. "Computer Design" by Sunggu Lee
XC4010XL CLB (Combinational Logic Block)
LookUp Table
(PROM or MUX)
"Computer Design" by Sunggu Lee

16. FPGA Configuration Methods
Use special “FPGA programmer” boards
with SRAM-based configuration, data is lost once the FPGA is extracted from the “FPGA programmer”
acceptable method for one-time programmable FPGAs
Attach PROM to FPGA in application board
store FPGA configuration in a serial PROM
FPGA needs to be re-configured when power is applied
Attach EPROM to FPGA in application board
Custom-designed FPGA programming interface
"Computer Design" by Sunggu Lee

17. FPGA Configuration S/W Support
Design Entry Tools
Schematic (drawing-based)
Language-based (e.g., ABEL, PALASM, VHDL)
Logic Simulation Tools
Functional simulation
Timing simulation (with back-annotated delay info.)
Shows timing diagram (or timing table) outputs
Logic Synthesis Tools
To create logic gate design from high-level description
To create configuration file (mapping to available gates and wires)
"Computer Design" by Sunggu Lee

18. FPGA Programming (Configuration)
Programming an FPGA from a Configuration File
Master / slave mode
master: FPGA chip is the initiator and controller of the FPGA configuration process
Serial / parallel mode
serial: configuration data is entered one bit at a time
Synchronous / asynchronous mode
synchronous: data entered in synch with a “clock” signal
"Computer Design" by Sunggu Lee

19. "Computer Design" by Sunggu Lee
Configuration Timing Waveforms
"Computer Design" by Sunggu Lee

20. Custom Designed FPGA Prog. H/W
Helps the user to understand the FPGA structure and configuration process (also low-cost solution)
Enables fast FPGA programming and test
Leads to fast prototyping
User can experiment with different solutions quickly
PC-based FPGA programming H/W solution
Uses PC’s parallel port interface
Uses simplest (default) configuration mode
slave, bit-serial, synchronous
"Computer Design" by Sunggu Lee

21. XC4010XL Programming Interface
3 mode pins to control programming mode
Leave (M0, M1, M2) pins unattached
These pins have default pull-up resistors (default (1,1,1) value)
Configuration clock pin
Used to control when config. data is clocked into chip
Make positive transition when data is stable
Configuration data input pins
D0 is the serial data input pin
Many pins have dual uses (for config. or normal mode)
Pins to check config. result (DOUT, PROGRAM, etc.)
"Computer Design" by Sunggu Lee

22. Using the PC Parallel Port Interface
Used to generate the signal waveforms required to program the FPGA with the “configuration data”
Kind of a general multi-bit waveform generator
Can be used to monitor several signals also
Parallel Port Interface Methods
Use SPP (Standard Parallel Port) based on original Centronics parallel printer port interface
Other, more flexible and general, interface modes available
"Computer Design" by Sunggu Lee

23. Generating Input Waveforms
Write data to a prespecified I/O port address
That data appears on the pins of the parallel port cable
3 port addresses used with the SPP mode
control, data, and status registers (3 8-bit registers)
write to a maximum of 12 output pins
read from a maximum of 9 input pins
ECR register (4th register) used to select SPP mode
Register addresses determined by the BIOS
Typically, LPT1 = 0378H = address of Data Register
"Computer Design" by Sunggu Lee

24. "Computer Design" by Sunggu Lee
* Figure 3.18:
Parallel Port
Interface Cct
= absolutely
necessary
connections
"Computer Design" by Sunggu Lee

25. "Computer Design" by Sunggu Lee
"Computer Design" by Sunggu Lee

26. "Computer Design" by Sunggu Lee
Expected Timing Waveforms
"Computer Design" by Sunggu Lee