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CORTEX-M0 Structure Discussion 1
ARM Cortex-M0 CORTEX-M0 Structure Discussion 1 August 21, 2012 Paul Nickelsberg Orchid Technologies Engineering and Consulting, Inc.
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Cortex-M0 Structure Discussion 1
Topics Today CORTEX-M0 Instruction Set CORTEX-M0 Memory Map CORTEX-M0 Register Set CORTEX-M0 Execution Modes
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ARM Cortex-M0 Instruction Map
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Memory Access Instructions
Mnemonic Instruction Description ADR Load PC Relative Address LDM Load Multiple Registers LDR Load Register (Numerous Types) POP Pop Registers from Stack PUSH Push Registers onto Stack STM Store Multiple Registers STR Store Register Cool Features: Multiple Registers may be accessed with a single instruction ADR allows easy relative addressing math
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Data Processing Instructions
Mnemonic Instruction Description ADCS Add with Carry ADD Add ANDS Logical AND ASRS Arithmetic Shift Right BICS Bit Clear CMN Compare Negative CMP Compare EORS Exclusive OR LSLS Logical Shift Left LSRS Logical Shift Right MOV Move
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Data Processing Instructions
Mnemonic Instruction Description MULS Multiply MVNS Move NOT ORRS Logical OR REV Reverse Byte Ordering in Word REV16 Reverse Byte Order in Short REVSH Reverse Byte Order in Short Sign Ext RORS Rotate Right RSBS Reverse Subtract SBCS Subtract with Carry SUBS Subtract SUBW
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Data Processing Instructions
Mnemonic Instruction Description SXTB Sign Extend SXTH UXTB Zero Extend UXTH TST Test Cool Features: 64-Bit Operations can be done w/two instructions Many options for Flag Updates Flexible comparisons
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Branch Instructions Mnemonic Instruction Description B(cc)
Branch Conditional BL Branch with Link BLX Branch Indirect with Link BX Branch Indirect Cool Features: Link features are like Z80 CALL/RET Instruction, LR Bit Set for proper POP{pc}
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Special Instructions Mnemonic Instruction Description BKPT Breakpoint
CPSID Disable Interrupts CPSIE Enable Interrupts DMB Data Memory Barrier DSB Data Synchronization Barrier ISB Instruction Synchronization Barrier MRS Move special register to register MSR Move register to special register NOP No Operation SEV Send Event
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Special Instructions Mnemonic Instruction Description SVC
Supervisor Call WFE Wait for Event WFI Wait for Interrupt Cool Features: Barrier Instructions SEV/SVC Instructions WFE/WFI Instructions
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Notable Missing Instructions
Mnemonic Instruction Description MLA Multiply with Accumulate SDIV Signed Divide SMLAL Signed Multiply w/Accumulate – 64-Bit Result SMULL Signed Multiply – 64-Bit Result Cortex-M0 is missing the Cortex-M3 instructions shown above. (Note: Cortex-M3 contains additional missing instructions not listed above)
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Cortex-M0 Memory Map Memory Region Usage Memory Region Size
Memory Region Start Memory Region Stop Device Access 511 Mbyte 0xE 0xFFFFFFFF Private Peripheral 1 Mbyte 0xE 0xE00FFFFF External Device 1 Gbyte 0xA 0xDFFFFFFF External Memory 0x 0x9FFFFFFF Internal Peripheral 512 Mbyte 0x 0x5FFFFFFF Internal SRAM 0x 0x3FFFFFFF Internal Code Execute 0x 0x1FFFFFFF
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Cortex-M0 Memory Types Memory Access Types Description NORMAL
CPU can re-order memory transactions for efficiency. CPU can perform speculative reads DEVICE CPU preserves transaction order relative to other transactions to DEVICE or STRONGLY-ORDERED memory STRONGLY-ORDERED CPU preserves transaction order relative to all other transactions Execute Never (XN) CPU is prevented from instruction execution, attempted instruction fetch causes HARDFAULT
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Cortex-M0 Memory Attributes
Memory Region Usage Memory Attribute XN Memory Region Start Memory Region Stop Device Access Device 0xE 0xFFFFFFFF Private Peripheral Strongly Ordered 0xE 0xE00FFFFF External Device 0xA 0xDFFFFFFF External Memory Normal -- 0x 0x9FFFFFFF Internal Peripheral 0x 0x5FFFFFFF Internal SRAM 0x 0x3FFFFFFF Internal Code Execute 0x 0x1FFFFFFF
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Cortex-M0 Core Registers
R Stack Pointer R Link Register R Program Counter Low Registers General Purpose Registers High Registers Stack Registers PSR – Program Status Register PRIMASK – Int Mask Register CONTROL – Control Register PSP MSP
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Cortex-M0 Registers Typical General Purpose Registers
13 General Purpose 32-Bit Regs Stack Pointer – (There are two!) Link Register Program Counter
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Cortex-M0 Registers Stack Registers PSP – Process Stack Pointer
MSP – Main Stack Pointer Selected by Bit 1 of CONTROL Register Unusual Feature in the 8-bit world
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Cortex-M0 Registers Special Registers PSP – Program Status Register
PRIMASK – Interrupt Mask Register CONTROL – Control Register PSP is a combination of sub-fields including flags, exception status, and T bit.
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Cortex-M0 Execution Modes
RESET Thread Mode Handler Mode Tail Chaining Late Arriving Exception Exception Return
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Cortex-M0 Execution Modes
Exception Types Exception Priority Reset Highest Priority -3 Non Maskable Interrupt (NMI) Priority -2 Hard Fault Priority -1 SVCall Configurable Priority PendSV SysTick Interrupt (IRQ)
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Cortex-M0 Execution Modes
RESET Thread Mode Handler Mode Exception Priority Check Push Stack Frame Vector Fetch Tail Chaining Late Arriving Exception Return Pop Stack Frame PSP/MSP Select
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Meaning and Implications
32-Bit CORTEX-M0 Processing Capability Instruction Set Multiple Move Features Multiply Features Large Flat Memory Map Memory Map Protected Areas Large 32-Bit Symmetric Registers Prioritized Interrupt Servicing Preemptive, Efficient Interrupt Structures 8-Bit Architecture Processor Architecture – 8-Bit World to 32-Bit World
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