1. CS 286 Computer Architecture & Organization
Pipeline Hazards
Department of Computer Science
Southern Illinois University Edwardsville
Fall, 2018
Dr. Hiroshi Fujinoki
Pipeline_Hazards/000

2. CS 286 Computer Architecture & Organization
Pipeline Hazards
Any anomalies that prevent a pipeline datapath
from functioning without pipeline stalls or flashes
Pipeline_Hazards/001

3. CS 286 Computer Architecture & Organization
Three Major Pipeline Hazards
1. Structural Hazards
2. Data Hazards
3. Control Hazards
Pipeline_Hazards/002

4. CS 286 Computer Architecture & Organization
1. Structural Hazards:
= pipeline hazards due to hardware resource conflicts
Example
Instruction fetch and data access
A processor instruction = [operator] + [parameters]
 instruction fetch
processor instruction:
sw $t1, 0($t2)
 save register to memory
// $t1  Mem[$t2+0]
Execution of this instruction requires two memory accesses
Pipeline_Hazards/003

5. CS 286 Computer Architecture & Organization
1. Structural Hazards (continued)
Main Memory
CPU Core
Unified Cache Architecture
Cache
Memory
CPU
Main Memory
CPU Core
Split Cache Architecture
Instruction
Cache
Data
CPU
Instruction code and data
need to take the same path
(i486)
Instruction code and data
take its own path
(Pentium and later)
Instruction code
Data
Pipeline_Hazards/004

6. CS 286 Computer Architecture & Organization
Unified Cache Architecture
Main Memory
CPU Core
Cache
Memory
CPU
Instruction code
Data
Memory address is accessed
and its content is loaded to
this processor
lw $t1, 0($t2) IF ID EX ME WB
// Mem[$t2+0]  $t1
instruction1
instruction2
instruction3 IF ID EX ME WB IF ID EX ME WB IF ID EX ME WB
These two memory-access
operations can not happen
at the same time
Instruction3 is now
“fetched” from memory IF ID EX ME WB
Pipeline_Hazards/005

7. CS 286 Computer Architecture & Organization
Resource Conflict IF ID EX ME WB IF ID EX ME WB
3 cycle stalls IF ID EX ME WB IF ID EX ME WB IF ID EX ME WB
Benefits from pipeline execution is lost
Pipeline_Hazards/006

8. CS 286 Computer Architecture & Organization
Worst case structural pipeline hazards IF ID EX ME WB
n-2 pipeline stalls IF ID EX ME WB IF ID EX ME WB IF ID EX ME WB
Pipeline Stalls
Pipeline_Hazards/007

9. CS 286 Computer Architecture & Organization
2. Data Hazards:
= pipeline hazards due data-dependency between instructions
Example
move $t1, $t // t1  t2
add $t3, $t1, // t3  t1 + 5
 
The same registers are used in more than
one instruction
Data Dependency
This can not be done IF ID EX ME WB
move $t1, $t2: IF ID EX ME WB
add $t3, $t1, 5:
Time
Pipeline_Hazards/008

10. CS 286 Computer Architecture & Organization
Data Dependency
move $t1, $t2: IF ID EX ME WB
add $t3, $t1, 5: IF ID EX ME WB
Resolve data dependency by stalls
move $t1, $t2: IF ID EX ME WB IF ID EX ME WB
add $t3, $t1, 5:
Pipeline stalls
Pipeline_Hazards/009

11. WB for “bne” instruction
CS 286 Computer Architecture & Organization
3. Control Hazards:
= pipeline hazards due to branch and jump instructions
Example: jump instructions
bne $s0, $s1, Next
instruction 1
  
Next: instruction 2
Pipeline flashes for control hazards
PC is set at the end of
WB for “bne” instruction
bne $s0, $s1, NEXT IF ID EX WB ME
instruction 1 IF ID EX ME WB
We can not start this
instruction here
Pipeline_Hazards/010

12. CS 286 Computer Architecture & Organization
3. Control Hazards:
= pipeline hazards due to branch and jump instructions
Example: jump instructions
bne $s0, $s1, Next
instruction 1
  
Next: instruction 2
Pipeline flashes for control hazards
PC is set at the end of
WB for “bne” instruction
bne $s0, $s1, Next IF ID EX WB ME
instruction 2 IF ID EX IF ID
Start fetching instruction 1
Pipeline Flashes
Pipeline_Hazards/010