1. Branching instructions
ARM instruction set
Data processing
instructions
Data transfer
Block transfer
Branching instructions
Multiply instructions
Software interrupt

2. Data Processing Instructions

3. Barrel Shifter in ARM processor is a functional unit testing that is used to perform the Shift and Rotate Operations.
Barrel Shifter provides five types of Shift and Rotate operations and they are :
Logical Shift Left (LSL)
Logical Shift Right (LSR)
Arithmetic Shift Right (ASR)
Rotate Right (ROR)
Rotate Right Extended (RRX)

4. This supports, but is not limited to:
Scaled addressing.
Multiplication by an immediate value.
Constructing immediate values.

5. Data Processing Instructions (2)
Arithmetic operations:
ADD, ADDC, SUB, SUBC, RSB, RSC
Bit-wise logical operations:
AND, EOR, ORR, BIC
Register movement operations:
MOV, MVN
Comparison operations:
TST, TEQ, CMP, CMN

6. Arithmetic Instructions
Syntax:
op{cond}{S} Rd, Rn, Operand2
op is one of ADD, SUB, RSB, ADC, SBC,or RSC.
cond is an optional condition code
S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation
If S is specified, these instructions update the N, Z, C and V flags according to the result.

7. Examples ADC add with carry
SBC Subt with borrow (unsigned or 2’s complement signed integers)
RSB Reverse subtraction
RSC = Reverse subtraction with borrow

10. Eg

12. Condition flags:
If S is specified, these instructions update the N, Z, C and V flags according to the result.
Use of r15
Examples:
ADD r2,r1,r3
SUBS r8,r6,#240 ; sets the flags on the result
RSB r4,r4,#1280 ; subtracts contents of r4 from 1280
ADCHI r11,r0,r3 ; only executed if C flag set and Z ; flag clear

14. Bitwise Logical Instructions
Syntax:
op{cond}{S} Rd, Rn, Operand2
op is one of AND, ORR, EOR, BIC.
cond is an optional condition code
S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation

15. Bitwise Logical Instructions
Condition flags:
If S is specified, these instructions:
update the N and Z flags according to the result
can update the C flag during the calculation of Operand2 
do not affect the V flag.

16. Bitwise logical instructions - egs
BIC – bit clear – Every 1 in the second operand clears the corresponding bit in the first operand

17. For reference

18. Bitwise logical instructions
V is unaffected as logical will not result in overflow

19. Register movement Instruction - egs
Two operand instruction – first is ignored
MVN – move negated
Negate second source and store in destn

20. Condition flags:
If S is specified, these instructions:
update the N and Z flags according to the result
can update the C flag during the calculation of Operand2 
do not affect the V flag.

21. Cmp= sub
Cmn = compare negative

22. CMP – whether s is set or not, it affects the flags
TEQ affects only Z N

23. Comparison Operations - egs
CMP r1, r2 ,• set cc on r1 - r2
;similar to sub but with a diff
CMN r1, r2 ; set cc on r1 + r2 // add (r1-(-r2))
TST r1, r2 ; set cc on r1 and r2
TEQ r1, r2 ; set cc on r1 xor r2
Cc – condition codes
Teq= test equivalence
Cmp will not store the results