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VECTOR MEDIAN VIDEO FILTER

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1 VECTOR MEDIAN VIDEO FILTER
SRI MOHAN KRISHNA DAVID SANDEEP Under the guidance of Mr. MATTIAS O’NILS

2 Introduction Noise filtering - The process of estimating the original image information from noisy data Vector median video filter is an Image restoration filter . Goal of image restoration- improve image in a predefined sense. Important aspect – having a prior knowledge of degradation phenomenon.

3 Basic function of a filter:
Restoration filter g(x,y) f(x,y) f(x,y) Ŋ(x,y) g(x,y) = f(x,y) + Ŋ(x,y) Restoration of f(x,y) form g(x,y) with a knowledge of Ŋ(x,y)

4 What is the need for a new filter?
Problem with averaging filter(mean filters) - Blurs edges and details in image. - Not effective for salt and pepper noise. Median filter: - Taking the median value instead of average or weighted average of pixels.  sort all the pixel values in an increasing order,take the middle one. - yeilds excellent results for images corrupted by salt and pepper noise

5 What is salt & pepper noise ?
a kind of impulsive noise Pa for z= a P(z) = Pb for z = b for others If Pa nearly eqaul to Pb and Pa,Pb ≠ 0 Then impulsive noise resembles salt and pepper noise Because of image digitization impulse noise tends to have extreme values i.e very large compared to strength of image signal P(z) Pb Pa z a b

6 Median filter: 3 x 3 square window
shape 100 200 205 203 195 100 100 100 100 100 100 100 200 100 100 100 100 195 100 100 100 100 100 100

7 Directional Vector Median Filter
S11 S22 S33 S22 S13 S31 S12 S22 S32 First Stage Median filter Second stage Median filter S21 S22 S23 s22 Medians are calculated in four directions resulting in four values In the second stage the median of the four values is calculated

8 Block diagram

9 1. Address Generator Data flow rsync rsync_o Address
1 1 rsync_o 1 1 Address 639 640 1 2 3 4 5 Genarates address where the input data is to be stored in block RAM’s

10 Block RAM’s address 1 2 3 4 5 639 640 Data_in = 20 Block RAM1 254 20 1
1 2 3 4 5 639 640 Data_in = 20 Block RAM1 254 20 1 1 1 1 1 1 Data_read1 254 Block RAM2 254 100 1 1 1 1 1 1 Data_read2 100 When read_write signal is enabled the data in the location specifed by address is read first and after that data to be written is placed in the location

11 Counter The counter counts the row and column values with reference to the frame synchronisation and row synchronisation pulses. Generates enable pulses for the edge detector block and dvmf evaluator block. If row synchronisation pulse turns high from low the column value is initialized 1. If row sync pulse is high the value of column is incremented for every clock pulse If frame synchronisation pulse changes high from low then row count is initialized to 1 Row count is incremented at row synchronisation positive edge transition. The enable signal is generated when column count >0 and < 641

12 Edge detector The edge detector detects the edges of the frame and informs to the DVMevaluator block If fsync is high ,it informs it as upper edge of the frame and initialises the row count value to 0. If rsync pulse changes from low to high it informs it as the left edge of frame and initialises the column count to 1 and increments row count. If rsync pulse changes from high to low it informs that it is the right edge of the frame If the row count = 480 then it informs that it is the bottom edge of the frame.

13 DVM Evaluator frame corner x Up/ Down Left / right 230 255 255 255
Pdata = 230 Pdata = 255 200 255 255 255 Data_read 1= 255 Data_read 1 = 200 x 200 255 Data_read 2 = X Up/ Down Left / right 200 170 180 255 150 200 100 130 210 215 200 150 255 200 180 210

14 results Noisy input image Matlab output VHDL output

15 Results The noise in the input image was removed successfully by the designed filter. Maximum Frequency: 51 MHz No of 641x8-bit dual-port block RAM’s used : 2 Number of 4 input LUTs :

16 Conclusion The obtained results are compared with the MAT LAB output and the results are found to be absolutely comparable. The only deviation obtained was at the first row where in the logic of VHDL specifies the first row output to be the pixel values of the last row of the previous frame. The customer requirement of 30 MHz frequency has been met successfully.

17 ?


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