1. ARM Introduction

2. The ARM7TDMI processor is a member of the Advanced RISC machine family of general purpose 32-bit microprocessor
What does mean ARM7TDMI ?
ARM bit Advanced RISC Machine
T - Thumb architecture extension
Two separate instruction sets, 32-bit ARM instructions and 16-bit Thumb instructions
D - Debug extension
M - Enhanced multiplier
I - Embedded ICE macrocell extension

3. Von Neumann Architecture
3-stage pipeline
fetch, decode, execute
32-bit Data Bus
32-bit Address Bus
37 32-bit registers
32-bit ARM instruction set
16-bit THUMB instruction set
32x8 Multiplier
Barrel Shifter

8. ARM operating states The ARM7TDMI processor has two operating states:
ARM state which executes 32-bit, word aligned ARM instructions
THUMB state which can execute 16-bit, halfword aligned THUMB instructions
Switching state
Entering THUMB state
BX instruction with the state bit (bit 0) set in the operand register.
Automatically on return from an exception (IRQ, FIQ, ABORT, SWI,…), if the exception was entered with the processor in THUMB state.
Entering ARM state
BX instruction with the state bit clear in the operand register.
Automatically on the processor taking an exception. In this case, the PC is placed in the exception mode’s link register.

9. ARM7TDMI Operating Modes
The ARM7TDMI supports seven modes of operation:
User (usr): The normal ARM program execution state
FIQ (fiq): Designed to support a data transfer or channel process
IRQ (irq): Used for general-purpose interrupt handling
Supervisor (svc): Protected mode for the operating system
Abort mode (abt): Entered after a data or instruction prefetch abort
System (sys): A privileged user mode for the operating system
Undefined (und): Entered when an undefined instruction is executed
Mode changes may be made under software control, or may be brought about by external interrupts or exception processing.
Most application programs will execute in User mode. The non-user modes' known as privileged modes-are entered in order to service interrupts or exceptions, or to access protected resources.

11. The ARM7TDMI has a total of 37 registers:
31 general-purpose 32-bit registers
6 status registers
These registers cannot all be seen at once. The processor state and operating mode dictate which registers are available to the programmer.

21. The THUMB state registers relate to the ARM state registers in the following way:

22. Program Status Registers (1/3)
The ARM7TDMI contains a Current Program Status Register (CPSR), plus five Saved Program Status Registers (SPSRs) for use by exception handlers.
These register's functions are:
Hold information about the most recently performed ALU operation
Control the enabling and disabling of interrupts
Set the processor operating mode

23. Condition Code Flags
The N, Z, C and V bits may be changed as a result of arithmetic and logical operations, and may be tested to determine whether an instruction should be executed
In ARM state, all instructions may be executed conditionally.
In THUMB state, only the Branch instruction is capable of conditional execution.
Control Bits
The I, F, T and M[4:0]) bits will be changed when an exception arises. If the processor is operating in a privileged mode, they can also be manipulated by software.
T bit:
This reflects the operating state. When this bit is set, the processor is executing in THUMB state, otherwise it is executing in ARM state. This is reflected on the TBIT external signal.
Note that the software must never change the state of the TBIT in the CPSR. If this happens, the processor will enter an unpredictable state.

24. Control Bits
Interrupt disable bits:
The I and F bits are the interrupt disable bits. When set, these disable the IRQ and FIQ interrupts respectively.
Mode bits:
The M4, M3, M2, M1 and M0 bits (M[4:0]) are the mode bits. These determine the processor's operating mode. Not all combinations of the mode bits define a valid processor mode. Only those explicitly described shall be used. The user should be aware that if any illegal value is programmed into the mode bits, M[4:0], then the processor will enter an unrecoverable state. If this occurs, reset should be applied.

25. Exceptions arise whenever the normal flow of a program has to be halted temporarily
For example to service an interrupt from a peripheral.
ARM supports 7 types of exception and has a privileged processor mode for each type of exception.
ARM Exception vectors

26. ARM organization Register file –
control
address register
Register file –
2 read ports, 1 write port + 1 read, 1 write port reserved for r15 (pc)
Barrel shifter – shift or rotate one operand for any number of bits
ALU – performs the arithmetic and logic functions required
Memory address register + incrementer
Memory data registers
Instruction decoder and associated control logic P C
incrementer PC
register
bank
instruction
decode A
multiply
& L
register U
control A B b u b b s u u s
barrel s
shifter
ALU
data out register
data in register
D[31:0]

27. Three-stage pipeline Fetch
the instruction is fetched from memory and placed in the instruction pipeline
Decode
the instruction is decoded and the datapath control signals prepared for the next cycle; in this stage the instruction owns the decode logic but not the datapath
Execute
the instruction owns the datapath; the register bank is read, an operand shifted, the ALU register generated and written back into a destination register

28. ARM single-cycle instruction pipeline

29. ARM single-cycle instruction pipeline
add r0,r1,#5
fetch
decode
fetch
execute add
decode
fetch
sub r2,r3,r6
execute sub
decode
cmp r2,#3
execute cmp
time 1 2 3

30. ARM multi-cycle instruction pipeline
Decode logic is always generating the control signals for the datapath to use in the next cycle

31. ARM development tools

32. ARM organization Register file –
control
address register
Register file –
2 read ports, 1 write port + 1 read, 1 write port reserved for r15 (pc)
Barrel shifter – shift or rotate one operand for any number of bits
ALU – performs the arithmetic and logic functions required
Memory address register + incrementer
Memory data registers
Instruction decoder and associated control logic P C
incrementer PC
register
bank
instruction
decode A
multiply
& L
register U
control A B b u b b s u u s
barrel s
shifter
ALU
data out register
data in register
D[31:0]

33. Data processing instruction datapath activity
Reg-Reg
Rd = Rn op Rm
r15 = AR + 4 AR = AR + 4
Reg-Imm
Rd = Rn op Imm
address register
increment
registers Rd Rn PC Rm
as ins.
as instruction
mult
data out
data in
i. pipe
address register
increment
registers Rd Rn PC
as ins.
as instruction
mult
data out
data in
i. pipe
[7:0]
(a) register – register operations
(b) register – immediate operations

34. SIR (store register) datapath activity.

35. STR (store register) datapath activity
Compute address
AR = Rn op Disp
r15 = AR + 4
Store data
AR = PC
mem[AR] = Rd<x:y>
If autoindexing => Rn = Rn +/- 4
address register
increment
registers Rn Rd
shifter = A
+ B /
- B
mult PC
byte?
data in
i. pipe
address register
increment PC
registers Rn
mult
lsl #0 = A / A
+ B / A
- B
[11:0]
data out
data in
i. pipe
(a) 1st cycle – compute address
(b) 2nd cycle – store data & auto-index

36. The first two (of three) cycles of a branch instruction.

37. The first two (of three) cycles of a branch instruction
Compute target address
AR = PC + Disp,lsl #2
Save return address (if required)
r14 = PC
AR = AR + 4
address register
increment
registers PC
lsl #2 = A
+ B
mult
data out
data in
i. pipe
[23:0]
address register
increment
registers
R14 PC
shifter = A
mult
data out
data in
i. pipe
Third cycle: do a small correction to the value stored in the link register in order that it points to directly at the instruction which follows the branch?
(a) 1st cycle – compute branch target
(b) 2nd cycle – save return address