1. 332:437 Lecture 16 FSM Synchronizers
Synchronization failure
Runt pulses
Simple synchronizers
Synchronizer timing
Handshake interface techniques
Summary
Material from An Engineering Approach to Digital Design, by William I. Fletcher, Englewood Cliffs, NJ: Prentice-Hall
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Bushnell: Digital Systems Design Lecture 16

2. Synchronization of Systems
Needed when merging independent systems on different clocks
Problem: System controller needs to know when or within what time frame it can expect input changes from controlled/controlling systems
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Bushnell: Digital Systems Design Lecture 16

3. Consequences of Synchronization Failure
Input Changes missed by system controller
Undefined state transitions occur
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Bushnell: Digital Systems Design Lecture 16

4. Input changing Near Triggering Edge of Clock
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Bushnell: Digital Systems Design Lecture 16

5. Output Cell in Meta-Stable Condition from “Runt” Pulse
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Bushnell: Digital Systems Design Lecture 16

6. Meta-Stable Condition of Flip-Flop
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Bushnell: Digital Systems Design Lecture 16

7. Example Synchronizer Catching Cell
Catching cell converts Pulse into level S D C R
7474
RET
F/F Q
SYSCLK(L)
RESET(L)
ASYN INPUT(L)
CATCHING
CELL
SYNCHD INPUT(H) +v
Q(H)
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Bushnell: Digital Systems Design Lecture 16

8. Synchronizer with Explicit Reset from System Controller+v
ASYN
INPUT(H)
Q(H) S D C R
7474
RET
F/F Q
RESET(L)
SYSCLK(L)
SYSTEM
CONTROLLERS
OUTPUT
DECODER
ASYN INPUT(L)
CATCHING
CELL OR
SYNCHD INPUT(H)
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Bushnell: Digital Systems Design Lecture 16

9. Synching Operation of the Pulse-Catching Circuits
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Bushnell: Digital Systems Design Lecture 16

10. Synchronizer Timing Considerations
May be impractical to increase system clock frequency for synchronization
Need to instead catch input pulse & hold it until system controller can service it.
fp – frequency of input pulse
fc – Clock frequency
tp – Period of input pulse
tc – Period of Clock
First assume that fp < fc
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Bushnell: Digital Systems Design Lecture 16

11. Synchronizer Based on These Assumptions
tp < tc So, tp short & infrequent in relation to system clock
State changes of system controller made on rising edge of system clock
Time period between falling & rising edge of system clock > system’s setting time
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Bushnell: Digital Systems Design Lecture 16

12. Bushnell: Digital Systems Design Lecture 16
Missed Short Asynchronous Input
Compared to system clock
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Bushnell: Digital Systems Design Lecture 16

13. Level Synchronization – When tp >> tc
Catching level that changes asynchronously with respect to system clock
Use same circuit as before, but omit catching cell
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Bushnell: Digital Systems Design Lecture 16

14. Problem with Asynchronous Inputs
Changes in inputs may cause outputs of next state decoder to change during set-up & hold times of flip-flops
Causes erratic behavior of present-state register
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Bushnell: Digital Systems Design Lecture 16

15. Handshake Interface Technique
One party stimulates second party
Second party signals first to acknowledge receipt of signal
First party can now initiate another transaction
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Bushnell: Digital Systems Design Lecture 16

16. Handshake Between Systems Operating Asynchronously
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Bushnell: Digital Systems Design Lecture 16

17. Bushnell: Digital Systems Design Lecture 16
Problem
Internal input changes in one of the systems being synchronized can cause transient electrical noise on output control lines.
May have to design special circuits to sense noise transient and delay action until it damps out.
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Bushnell: Digital Systems Design Lecture 16

18. Bushnell: Digital Systems Design Lecture 16
Summary
Synchronization failure
Runt pulses
Simple synchronizers
Synchronizer timing
Handshake interface techniques
4/10/2019
Bushnell: Digital Systems Design Lecture 16