1. Design Service
Heung-Joon Park
Director
Design Support

2. CONTENTS
Physical Design Support
Analog/Mixed-Signal
Embedded Memory

3. Physical Design Support
Physical Design Verification Service
Library Service
COT Process Service

4. Rule Decks for Physical Verification

5. Layout vs. Silicon Correlation
RC Extraction for Physical Verification
Example: Inverter ring oscillator
Propagation Delay per Stage
w=0.42um, l=0.21um, Temp=27℃

6. Cell Library Solution aa2533C07.A Avant! Passport library Now
aa2533C07.A Virtual Silicon Diplomat library Now
aa1833C07.0 Synopsys process optimized
Low power Odyssey library Q/99
aa2533C07.A Synopsys process optimized
High performance Odyssey library Q/99

7. Cell Library Service for COT
Enable broad access to aa2533C07.A & aa1833C07.0
technologies through license agreements with
multiple library suppliers
License Process specific library for each process
technology
Assist customers in porting customer owned
libraries to process technologies

8. COT Process Service Objective: Requirements:
First two masks ready within 4 days
from receiving Customer Database
Requirements:
Design Rule Check - No errors
Customer Database & Tooling Information (CDTI)
completed and delivered 2 days prior to database

9. Mask Making Service Flow
Time minus 2 Days
CDTI - in
GDS II Database transfer
Customer
Time Zero
D/B check with CDTI No
Feedback
Yes
OPC Processing
(OPC)
Anam
Data back-up
by Encryption
Mask Pattern Generation
(PG)
Time plus 2 Days
Pattern transfer to Mask Vendor
Time plus 4 Days
Mask delivery to FAB
(First two layers)
Mask vendor

10. Analog/Mixed Signal Blocks
Phase Locked Loop
Analog to Digital / Digital to Analog Converter

11. Mixed-signal(PLL) Library
RF Frequency Synthesis
Timing Recovery
Clock Synthesis
Freq. Synthesis PLL with a Spiral Inductor
Freq. Synthesis PLL with a Spiral Inductor
Application Area
Clock Recovery PLL
Clock Recovery PLL
Clock Synthesis PLL for RAMBUS DRAM
Clock Synthesis PLL(50~500MHz)
Clock Synthesis PLL(50~500MHz)
Q Q Q Q Q Q Q Q
aa2533C07.A IP
aa1833C07.0 IP

12. Mixed-signal(ADC/DAC) Library
100 MSPS
10 MSPS
1 MSPS
100 kSPS
Current Steering DAC( 100 MSPS / 8 Bit )
Folding Interpolation ADC( 30 MSPS / 8/10 Bit )
Architecture
Folding Interpolation ADC( 30 MSPS / 8/10 Bit )
Sigma-Delta ADC(1MSPS / 13bit)
1999 1Q Q Q Q Q Q Q Q
aa2533C07.A IP
aa1833C07.0 IP

13. Memory Generator Suppliers
Embedded Memory
Memory Generator Suppliers
SYNOPSYS
Virtual Silicon
Avant!
Mentor Graphics

14. Availability aa2533C07.A Technology aa1833C07.0 Technology
- Synopsys: 4Q ‘99
- Virtual Silicon: NOW
- Avant!: NOW
- Mentor Graphics: 2Q ‘99
aa1833C07.0 Technology
- Synopsys: 3Q ‘99
- Mentor Graphics: 1Q ‘00

15. SYNOPSYS aa2533C07.A High Performance - Single Port Synchronous SRAM
- Dual Port Synchronous SRAM
- ROM
aa1833C07.0 Low Power
- Single Port Synchronous SRAM
- Dual Port Synchronous SRAM
- ROM

16. SYNOPSYS (cont’d) Synchronous SRAM Technology aa2533C07.A aa1833C07.0
Ports
Single
Dual
Single
Dual
Max. Size
256Kbits
256Kbits
256Kbits
256Kbits
Bits Range
2 ~ 32
2 ~ 32
2 ~ 32
2 ~ 32
Words Range
32 ~ 8K
32 ~ 8K
32 ~ 8K
32 ~ 8K
Access Time*
3.34ns
3.36ns
2.52ns**
2.75ns**
* Memory Size = 4k x 16
** Measured at 1.62V

17. Virtual Silicon aa2533C07.A High Performance
- Single Port Synchronous SRAM
- Two Port Synchronous SRAM

18. Virtual Silicon (Cont’d)
Synchronous SRAM
Technology
aa2533C07.A
Ports
Single
Two
Max. Size
512Kbits
256Kbits
Bits Range
2 ~ 64
2 ~ 64
Words Range
16 ~ 8k
16 ~ 8k
Access Time*
2.5ns
3.3ns
* Memory Size = 4k x 16

19. Avant! aa2533C07.A High Performance - Single Port Asynchronous SRAM
- Dual Port Asynchronous SRAM
- Two Port Asynchronous SRAM
- Single Port Synchronous SRAM
- Synchronous ROM

20. Avant! (cont’d) Asynchronous SRAM Technology aa2533C07.A Ports Single
Dual
Two
Max. Size
128Kbits
64Kbits
36Kbits
Bits Range
8 ~ 36
4 ~ 36
2 ~ 36
Words Range
16 ~ 4K
32 ~ 8K
64 ~ 2K
Access Time
3.07ns*
3.94ns**
3.7ns***
* Memory Size = 4k x 16
** Memory Size = 2k x 4
*** Memory Size = 2k x 16

21. Avant! (cont’d) Synchronous SRAM/ROM Technology aa2533C07.A Type SRAM
Max. Size
144Kbits
512Kbits
Bits Range
4 ~ 36
4 ~ 72
Words Range
32 ~ 8k
64 ~ 8k
Access Time*
3.96ns*
3.34ns**
* Memory Size = 4k x 36
** Memory Size = 8k x 72

22. Single port Synchronous SRAM
Mentor Graphics
Single port Synchronous SRAM
Technology
aa2533C07.A
Max. Size
128Kbits
4Mbits
Bits Range
1 ~ 128
1 ~ 512
Words Range
4 ~ 8k
8 ~ 32k
Access Time
3.1ns*
5ns**
Cell Size
10.8um2
10.8um2
* Memory Size = 2k x 64
** Memory Size = 32k x 32

23. Mentor Graphics (cont’d) Mega-memory Symbol & Truth Table
CLK
CSB
RWB
OEB
ADDR
DIN
Mega-bit
Synchronous
Single Port
SRAM Generator
N Words
M Bits
0-(log2N-1)
0-(M-1)
DOUT
COMMENTS
OEB is uncondi-
tional tri-state
De-selected
Precharge
Write Mode
Read Mode
CLK CSB RWB OEB ADDR DIN DOUT x 1 z
Valid
=DIN
Stored
Data
Symbol
Truth Table

24. EDA Tool Support Synopsys Virtual Silicon Avant! Mentor - Verilog/VHDL
- PrimeTime
- Composer
- Cadence(Floorplan)
- Silicon Ensemble
- Apollo
-GDSII
- Synopsys Tools
- Verilog/VHDL
- Design Compiler
- PrimeTime
- Silicon Ensemble
- Aquarius-XO
- GDSII
- Verilog/VHDL
- Compass tool
- GDSII
- Verilog/VHDL
- GDT
- Synopsys
- Pathmill
- Critical Path netlist
- GDSII
- HTML Datasheet

25. Plan
Memory BIST
Memory Redundancy
Migrate to aa1833C07.0