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Pipelining: critical path, pipeline hazards Prof. Eric Rotenberg

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1 Pipelining: critical path, pipeline hazards Prof. Eric Rotenberg
ECE 463/563 Fall `18 Pipelining: critical path, pipeline hazards Prof. Eric Rotenberg Fall 2018 ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg

2 ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg
Critical Path Critical path Longest delay (logic and wire delay) between any two flip-flops (Q output to D input) Dictates the minimum cycle time (clock period), hence, maximum clock frequency Going from unpipelined datapath to pipelined datapath reduces cycle time Deeper pipelining reduces cycle time even further Fall 2018 ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg

3 ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg
Fall 2018 ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg

4 ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg
Fall 2018 ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg

5 ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg
Example #1 Unpipelined datapath: Critical path = 50 ns THEREFORE: CT ≥ 50 ns (freq ≤ 20 MHz) Pipelined datapath: “Local” critical path of IF stage: 10 ns “Local” critical path of ID stage: 10 ns “Local” critical path of EX stage: 10 ns “Local” critical path of MEM stage: 10 ns “Local” critical path of WB stage: 10 ns (Notice = 50) THEREFORE: CT ≥ 10 ns (freq ≤ 100 MHz) Somewhat idealistic Stages are perfectly balanced in this example! Fall 2018 ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg

6 ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg
Example #2 Unpipelined datapath: Critical path = 50 ns THEREFORE: CT ≥ 50 ns (freq ≤ 20 MHz) Pipelined datapath: “Local” critical path of IF stage: 10 ns “Local” critical path of ID stage: 12 ns “Local” critical path of EX stage: 8 ns “Local” critical path of MEM stage: 13 ns “Local” critical path of WB stage: 7 ns (Notice = 50) THEREFORE: CT ≥ 13 ns (freq ≤ 77 MHz) STILL somewhat idealistic Ignores delay of intervening pipeline registers! Latches/flip-flops have delay: overhead of pipelining Fall 2018 ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg

7 ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg
Example #3 Unpipelined datapath: Critical path = 50 ns THEREFORE: CT ≥ 50 ns (freq ≤ 20 MHz) Pipelined datapath: Assume worst-case flip-flop delay is 1 ns “Local” critical path of IF stage: 11 ns “Local” critical path of ID stage: 13 ns “Local” critical path of EX stage: 9 ns “Local” critical path of MEM stage: 14 ns “Local” critical path of WB stage: 8 ns (Notice = 55) THEREFORE: CT ≥ 14 ns (freq ≤ 71 MHz) Fall 2018 ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg

8 ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg
cycle Unpipelined datapath: Long cycle time (CT) CPI = 1 Example: CT=50ns TPI=CPI*CT =1*50 =50ns/instr. 1 2 i IF ID EX MEM WB i+1 i+2 instr. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 i IF ID EX MEM WB i+1 i+2 Pipelined datapath, but no instr. overlap: Short cycle time (CT) CPI = 5 Example: CT=10ns TPI=CPI*CT =5*10 =50ns/instr. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 i IF ID EX MEM WB i+1 i+2 Pipelined datapath, instr. overlap: Short cycle time (CT) CPI = 1 (pipelining) Example: CT=10ns TPI=CPI*CT =1*10 =10ns/instr. Fall 2018 ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg

9 Summary: Pipelined RISC-V
Isolate each of IF, ID, EX, MEM, WB with latches or flip-flops (“pipeline registers”) When instruction i is in WB, i+1 is in MEM, etc. Graphically: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 i IF ID EX MEM WB i+1 i+2 i+3 i+4 i+5 Fall 2018 ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg

10 ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg
Pipeline Hazards A hazard reduces the performance of the pipeline Three kinds: Structural hazards: Not enough hardware resources for all combinations of concurrent instructions Control hazards: Mispredicted branches incur a misprediction penalty Data hazards: Dependencies between instructions prevent their overlapped execution Fall 2018 ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg

11 ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg
Structural Hazards Uncommon for our pipeline example Consider a pipeline with a unified data+instruction cache: uses cache 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A (a load) IF ID EX MEM WB B C D stall E F make instr. D wait (cache resource busy) Fall 2018 ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg

12 ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg
Control Hazards A: bne r1,r2,X B: … C: … D: … E: … … X: … Y: … Suppose r1 != r2 (branch is taken) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A IF ID EX MEM WB B - C D X Y squash redirect PC = PC+4 (sequential) not always correct Taken branch incurs 3-cycle penalty Fall 2018 ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg

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