1. Multi-Cycle Datapath
Lecture notes from MKP, H. H. Lee and S. Yalamanchili

2. Reading Appendices A.7, D.3, D.4, D.5
Note: Appendices A-E in the hardcopy text correspond to chapters 7-11 in the online text.
Practice Problems: 15, 16, 22

3. Morgan Kaufmann Publishers
10 April, 2019
Single Cycle Datapath
Longest instruction
Sharing hardware
What are the performance limitations of this datapath?
cycle time
clk
Chapter 4 — The Processor

4. Why Multi-Cycle? Single cycle datapath Multi-cycle datapth
Instruction Class
Instruction Fetch
Register Read
ALU Operation
Data Access
Register Write
Total Time
Load word
2ns
1ns
8ns
Store word
7ns
R-format
6ns
Branch
5ns
Single cycle datapath
Design for the worst case!
Need to make the cycle time = 8ns per cycle
Multi-cycle datapth
Design for each individual instruction class
For the above example: cycle time = 2ns
Lw=10ns (5 cycles), sw=8ns (4 cycles), R-format=8ns(4 cycles), beq=6ns (3 cycles)

5. Multi-Cycle Approach
Break up the instructions into steps, each step takes a clock cycle
Balance the amount of work to be done
Restrict each cycle to use only one major functional unit
At the end of a cycle
Store values for use in later cycles (easiest thing to do)
Introduce additional “internal” registers

6. Instruction Execution Steps
Register-Register Instruction
Fetch Instruction
Decode Instruction
ALU Operation
Write Register
Memory Read Instruction
Fetch Instruction
Decode Instruction
Address Calculation
Memory Read
Write Register
Memory Write Instruction
Fetch Instruction
Decode Instruction
Address Calculation
Memory Write
Branch Instruction
Different instructions perform different operations at this step
Fetch Instruction
Decode Instruction
Branch Test & PC Update
clk
cycle time
Start instruction fetch
Complete instruction fetch

7. Control Flow instructions
Functional Behavior IF
Instruction Fetch ID
Instruction Decode
Control Flow instructions
Memory instructions
Addr
ALU Br J
Instruction Execute
MRd
MWr
Memory
ALU instructions
RWr
RWr
Register Writeback

8. New internal registers
Multi-Cycle Datapath
Fetch Instruction
Decode Instruction
Addr Calc
ALU OP
Branch
Test S h i f t l e 2 M m o R g I r D a d W P C y u x 1 s n c [ 5 – ] 4 A L U O p B 3 6 Z
New internal registers
Write Register
Memory Read/Write

9. Complete Control Lines
When to write
What to write P C W r i t e C o n d P C S o u r c e P C W r i t e I o r D O u t p u t s A L U O p A L U S r c B M e m R e a d A L U S r c A M e m W r i t e C o n t r o l M e m t o R e g R e g W r i t e I R W r i t e O p R e g D s t [ 5 – ] M 2 6 2 8 J u m p 1 u I n s t r u c t i o n [ 2 5 – ] S h i f t a d d r e s s [ 3 1 - ] x l e f t 2 2 I n s t r u c t i o n [ 3 1 - 2 6 ] P C P C [ 3 1 - 2 8 ] M I n s t r u c t i o n R e a d u A d d r e s s [ 2 5 – 2 1 ] r e g i s t e r 1 M u x R e a d A x 1 M e m o r y I n s t r u c t i o n R e a d d a t a 1 1 Z e r o [ 2 – 1 6 ] r e g i s t e r 2 M e m D a t a A L U R e g i s t e r s A L U A L U O u t I n s t r u c t i o n M W r i t e r e s u l t [ 1 5 – ] I n s t r u c t i o n u r e g i s t e r R e a d B d a t a 2 W r i t e I n s t r u c t i o n [ 1 5 – 1 1 ] x d a t a W r i t e 4 1 M r e g i s t e r 1 d a t a u 2 x I n s t r u c t i o n 3 [ 1 5 – ] M u x M e m o r y 1 d a t a 1 6 3 2 S h i f t A L U r e g i s t e r S i g n e x t e n d l e f t 2 c o n t r o l I n s t r u c t i o n [ 5 – ]

10. Five Execution Steps Instruction Fetch (IF)
Instruction Decode and Register Fetch (ID)
Execution, Memory Address Computation, or Branch Completion (EX)
Memory Access or R-type instruction completion (MEM)
Write-back step (WB)

11. Instruction Fetch Control IR = Memory[PC]; PC+=42 P C M u x 1 R g s r W d a I n c o [ 5 – ] 4 3 6 A L U Z m y B D O p - J 8

12. Instruction Fetch (IF)
Use PC to get instruction and put it in the Instruction Register.
Increment the PC by 4 and put the result back in the PC.
Can be described succinctly using RTL "Register-Transfer Language" IR = Memory[PC]; PC = PC + 4; Can we figure out the values of the control signals?
IR = Memory[PC]; MemRead=1; IRWrite=1; IorD=0;
PC = PC + 4; ALUSrcA=0; ALUSrcB=01; ALUOp=00 (add); PCSource=00; PCWrite=1

13. ID Stage: Assign A and B; Calculate Branch Addressf t l e 2 P C M u x 1 R g s r W d a I n c o [ 5 – ] 4 3 6 A L U Z m y B D O p - J 8

14. Instruction Decode and Register Fetch (ID)
Still do not have any idea what instruction it is.
Read registers rs and rt in case we need them
Compute the branch address (used in next cycle in case the instruction is a branch)
RTL: A = Reg[IR[25-21]]; B = Reg[IR[20-16]]; ALUOut = PC + (sign-extend(IR[15-0]) << 2);
ALUSrcA = 0; ALUSrcB = 11; ALUOp = 00 (add); (for branch target)

15. Execute: Memory Type ALUOut = A + offset (address)h i f t l e 2 P C M u x 1 R g s r W d a I n c o [ 5 – ] 4 3 6 A L U Z m y B D O p - J 8

16. Execute: R- Type ALUOut = A op BS h i f t l e 2 P C M u x 1 R g s r W d a I n c o [ 5 – ] 4 3 6 A L U Z m y B D O p - J 8

17. Execute: Branch Type if (A==B) PC=ALUOutS h i f t l e 2 P C M u x 1 R g s r W d a I n c o [ 5 – ] 4 3 6 A L U Z m y B D O p - J 8

18. Execute: Jump Type (New PC)S h i f t l e 2 P C M u x 1 R g s r W d a I n c o [ 5 – ] 4 3 6 A L U Z m y B D O p - J 8

19. Execute, memory or branch (EX: instruction dependent)
The first cycle, the operation is determined by the instruction class
ALU is performing one of the following functions, based on instruction type
Memory Reference: ALUOut = A + sign-extend(IR[15-0]); ALUSrcA=1; ALUSrcB=10; ALUop=00 (add)
R-type: ALUOut = A op B; ALUSrcA=1; ALUSrcB=00; ALUop=10 (funct, inst[5:0], decides op)
Branch: if (A==B) PC = ALUOut;
PCSource=01; ALUSrcA=1; ALUSrcB=00; ALUop=01 (sub); PCWriteCond=1; PCWrite=0;
Jump: PC = {PC[31:28] || IR[25:0] || 2‘b00};
PCSource=10; PCWrite=1;

20. MEM: Load S h i f t l e 2 P C M u x 1 R g s r W d a I n c o [ 5 – ] 41 R g s r W d a I n c o [ 5 – ] 4 3 6 A L U Z m y B D O p - J 8

21. MEM: Store S h i f t l e 2 P C M u x 1 R g s r W d a I n c o [ 5 – ] 41 R g s r W d a I n c o [ 5 – ] 4 3 6 A L U Z m y B D O p - J 8

22. Memory Access or R-Type
Loads and stores access memory MDR = Memory[ALUOut];IorD=1; MemRead=1;
or Memory[ALUOut] = B; IorD=1; MemWrite=1
R-type instructions finish Reg[IR[15-11]] = ALUOut; RegDst=1; MemtoReg=0;
RegWrite =1

23. R-Type Completion S h i f t l e 2 P C M u x 1 R g s r W d a I n c o [1 R g s r W d a I n c o [ 5 – ] 4 3 6 A L U Z m y B D O p - J 8

24. Memory Access or R-Type
Loads and stores access memory MDR = Memory[ALUOut];IorD=1; MemRead=1;
or Memory[ALUOut] = B; IorD=1; MemWrite=1
R-type instructions finish Reg[IR[15-11]] = ALUOut; RegDst=1; MemtoReg=0;
RegWrite =1

25. WB for Load S h i f t l e 2 P C M u x 1 R g s r W d a I n c o [ 5 – ]1 R g s r W d a I n c o [ 5 – ] 4 3 6 A L U Z m y B D O p - J 8

26. Write-back for load operation
Reg[IR[20-16]]= MDR; MemtoReg=1; RegWrite=1; RegDst=0;
What about all the other instructions?

27. Summary
Example:

28. Multi-Cycle Datapath Programs take only as long as they need to
Variable timing per instruction
Pick a base cycle time
Re-use hardware
Avoid unnecessary duplication of hardware
Revisit control
Combinational vs. state machine design

29. Simple Questions
How many cycles will it take to execute this code? lw $t2, 0($t3) lw $t3, 4($t3) beq $t2, $t3, Label #assume not add $t5, $t2, $t3 sw $t5, 8($t3) Label: ...
What is going on during the 8th cycle of execution?
In what cycle does the actual addition of $t2 and $t3 takes place?
Example:

30. Implementing the Control (D.3)
Value of control signals is dependent upon:
What instruction is being executed
Which step is being performed
Use the information we have accumulated to specify a finite state machine
Specify the finite state machine graphically, or
Use microprogramming
Implementation can be derived from specification

31. Graphical Specification of FSMW r i t e S o u c = 1 A L U B O p n d R g D s M m I a f h / J l E x y - b k ( ' ) 1 S t a r t ) - t y p e ) Q ' E ) J ' = ' B ' = O p p ( O ( 2 6 8 9 ( ) O ' p W = L ' ' S = W ' ) p O ( 3 5 7 4

32. Control Signals: Truth Table

33. Finite State Machine for ControlP C W r i t e P C W r i t e C o n d I o r D M e m R e a d
Control Logic M e m W r i t e I R W r i t e
Alternatives for implementing the control logic? M e m t o R e g P C S o u r c e
Outputs A L U O p A L U S r c B A L U S r c A R e g W r i t e R e g D s t N S 3 N S 2
Inputs N S 1 N S 5 4 3 2 1 p p p p p p 3 2 1 O O O O O O S S S S I n s t r u c t i o n r e g i s t e r S t a t e r e g i s t e r o p c o d e f i e l d

34. Sequencer Implementation (D.4)
Sequence through the state machine
What are my options?
Control branches in the state machine via dispatch tables

35. Control Flow Sequencing Options P C W r i t e S o u c = 1 A L U B O pA L U B O p n d R g D s M m I a f h / J l E x y - b k ( ' )

36. Control Implementation

37. Final Contents of Control ROM
Separation of control flow and data

38. Specifying Control
Specifying all of the control bits for each state is tedious and error prone
Use a symbolic language
Each state is a microinstruction
Organize the control bits into fields  microinstruction
Microprograms, microcode, and microprogramming
ALU Control
SRC Control
REG Control
MEM Control
PC Control
Sequencing

39. Microinstruction format

40. Microprogramming A specification methodology
appropriate if hundreds of opcodes, modes, cycles, etc.
signals specified symbolically using microinstructions
Will two implementations of the same ISA architecture have the same microcode?
What would a micro-assembler do?
microinstruction
ISA Interpreter

41. Microcode: Trade-offs
Specification Advantages:
Easy to design and write
Design architecture and microcode in parallel
Implementation (off-chip ROM) Advantages
Easy to change since values are in memory
Can emulate other architectures
Can make use of internal registers
Implementation Disadvantages, SLOWER now that:
Control is implemented on same chip as processor
ROM is no longer faster than RAM
No need to go back and make changes

42. Study Guide Given a MIPS 32 instruction sequence
Reproduce the sequence of states generated by the controller
Compute the execution time in cycles
Determine all control signal values if the system is frozen at an arbitrary clock cycle e.g., state
Modify the datapath and state machine to
Add new instructions
Extend the memory system where an access takes 2 cycles instead of 1 cycle
Draw the multicycle datapath from memory

43. Glossary Dispatch table Finite State Machine Instruction decode
Instruction fetch
Microinstruction
Microprogramming
Microcode
Multi-Cycle datapath
Sequencer
ROM