2. Review Fig 4.15 page 320 / Fig. 4.17 page 322
Review Timing

3. Multicycle Implementation
Realistic Approach
Enables time sharing functional units during an
instruction ( Memory and ALU)
Enables instructions to be implemented with different
number of clock cycles

4. Multicycle Implementation
Assumptions:
Each STEP in the execution will take 1 clock cycle

5. Multicycle Implementation
Assumptions:
Each STEP in the execution will take 1 clock cycle
Each of these operations require 1 clock cycle
- Memory Access ( Idealized)
- Register File Access
- An ALU Operation

6. Multicycle Implementation
Assumptions:
Each STEP in the execution will take 1 clock cycle
Each of these operations require 1 clock cycle
- Memory Access ( Idealized)
- Register File Access
- An ALU Operation
Any Data produced by these must be held in a register
to be used in a later cycle

7. IR timing requires a write control signalD a t a P C A d d r e s s IR A R e g i s t e r # I n s t r u c t i o n M e m o r y R e g i s t e r s A L U A L U O u t o r d a t a M e m o r y R e g i s t e r # d a t a B D a t a r e g i s t e r R e g i s t e r #
MDR
IR timing requires a write control signal

8. Processor Design Process
Processor (Instruction Set Architecture)
Datapath Control
Mem Reg File ALU Mux Reg Decoder Sequencer
Gates

9. Processor Design Process
Processor (Instruction Set Architecture)
Datapath Control
Register Transfer
Sequence
Mem Reg File ALU Mux Reg Decoder Sequencer
Gates

10. STATE Register Transfers NEXT STATE
S0 M[PC] IR, PC+4 PC, S1 S
S1 R[IR[25-21]] A, S2 S
S2 A + sign_ext(IR[15-0]) ALUOut, S3 S
S3 M[ ALUOut] MDR, S4 S
S MDR R[ IR[20-16]], S0 S

11. MIPS - Lite
Consider the following instructions for implementation
INSTRUCTION OP FUNCT
R type
add
subtract
AND OR
set on less than 0 42
load word na
store word na
branch equal 4 na

12. Basic steps all instructions execute
Access the Instruction from Memory
Decode Instruction and Access the Data
from Registers
3. Perform the Instruction
4. Write the Result

13. For Multicycle Design
Define S = S0 , S1 , S2 , ..., Sn
Where S is the STATE of the processor.
Sk denotes that S decodes to k

14. Load Word & Store Word ( I – type )
lw rt, imm16 (rs) or sw rt, imm16 ( rs)
op rs rt address/ immediate
31, , 25, , 20, , 15,
lw # load word
M[ R[rs] + sign_ext(imm16) ] R[rt]
sw # store word
R[rt] M[ R[rs] + sign_ext(imm16) ]

15. lw rt, imm16 (rs) # load word
M[ R[rs] + sign_ext(imm16) ] R[rt]
For Op = ‘LW’ Next State
S0 M[PC] IR, PC+4 PC, S1 S

16. IR timing requires a write control signalD a t a P C A d d r e s s IR A R e g i s t e r # I n s t r u c t i o n M e m o r y R e g i s t e r s A L U A L U O u t o r d a t a M e m o r y R e g i s t e r # d a t a B D a t a r e g i s t e r R e g i s t e r #
MDR
IR timing requires a write control signal

17. lw rt, imm16 (rs) # load word
M[ R[rs] + sign_ext(imm16) ] R[rt]
For Op = ‘LW’
S0 M[PC] IR, PC+4 PC, S1 S
S1 R[IR[25-21]] A, S2 S

18. IR timing requires a write control signalD a t a P C A d d r e s s IR A R e g i s t e r # I n s t r u c t i o n M e m o r y R e g i s t e r s A L U A L U O u t o r d a t a M e m o r y R e g i s t e r # d a t a B D a t a r e g i s t e r R e g i s t e r #
MDR
IR timing requires a write control signal

19. lw rt, imm16 (rs) # load word
M[ R[rs] + sign_ext(imm16) ] R[rt]
For Op = ‘LW’
S0 M[PC] IR, PC+4 PC, S1 S
S1 R[IR[25-21]] A, S2 S
S2 A + sign_ext(IR[15-0]) ALUOut, S3 S

20. lw rt, imm16 (rs) # load word
M[ R[rs] + sign_ext(imm16) ] R[rt]
For Op = ‘LW’
S0 M[PC] IR, PC+4 PC, S1 S
S1 R[IR[25-21]] A, S2 S
S2 A + sign_ext(IR[15-0]) ALUOut, S3 S
S3 M[ ALUOut] MDR, S4 S

21. lw rt, imm16 (rs) # load word
M[ R[rs] + sign_ext(imm16) ] R[rt]
For Op = ‘LW’
S0 M[PC] IR, PC+4 PC, S1 S
S1 R[IR[25-21]] A, S2 S
S2 A + sign_ext(IR[15-0]) ALUOut, S3 S
S3 M[ ALUOut] MDR, S4 S
S MDR R[ IR[20-16]], S0 S

22. lw rt, imm16 (rs) # load word
M[ R[rs] + sign_ext(imm16) ] R[rt]
For Op = ‘LW’
S0 M[PC] IR, PC+4 PC, S1 S
S1 R[IR[25-21]] A, S2 S
S2 A + sign_ext(IR[15-0]) ALUOut, S3 S
S3 M[ ALUOut] MDR, S4 S
S MDR R[ IR[20-16]], S0 S
sw rt, imm16 ( rs) # store word
R[rt] M[ R[rs] + sign_ext(imm16) ]
What’s different?

23. lw rt, imm16 (rs) # load word
M[ R[rs] + sign_ext(imm16) ] R[rt]
For Op = ‘LW’
S0 M[PC] IR, PC+4 PC, S1 S
S1 R[IR[25-21]] A, R[IR[20-16]] B S2 S
S2 A + sign_ext(IR[15-0]) ALUOut, S3 S
S3 M[ ALUOut] MDR, S4 S
S MDR R[ IR[20-16]], S0 S
sw rt, imm16 ( rs) # store word
R[rt] M[ R[rs] + sign_ext(imm16) ]
What’s different?

24. sw rt, imm16 ( rs) # store word
R[rt] M[ R[rs] + sign_ext(imm16) ]
For Op = ‘SW’
S0 M[PC] IR, PC+4 PC, S1 S
S1 R[IR[25-21]] A, R[IR[20-16]] B S2 S
S2 A + sign_ext(IR[15-0]) ALUOut, ? S

25. sw rt, imm16 ( rs) # store word
R[rt] M[ R[rs] + sign_ext(imm16) ]
For Op = ‘SW’
S0 M[PC] IR, PC+4 PC, S1 S
S1 R[IR[25-21]] A, R[IR[20-16]] B S2 S
S2 A + sign_ext(IR[15-0]) ALUOut, S5 S
S5 B M[ ALUOut], S0 S

26. IR timing requires a write control signalD a t a P C A d d r e s s IR A R e g i s t e r # I n s t r u c t i o n M e m o r y R e g i s t e r s A L U A L U O u t o r d a t a M e m o r y R e g i s t e r # d a t a B D a t a r e g i s t e r R e g i s t e r #
MDR
IR timing requires a write control signal

27. R – Arithmetic – Logic Instruction
op rd, rs, rt
R[rs] op R[rt] R [rd]
op rs rt rd shamt funct

28. R – Arithmetic – Logic Instruction
op rd, rs, rt
R[rs] op R[rt] R [rd]
Op = R-type
S0 M[PC] IR, PC PC, S S

29. R – Arithmetic – Logic Instruction
op rd, rs, rt
R[rs] op R[rt] R [rd]
Op = R-type
S0 M[PC] IR, PC PC, S S
S1 R[IR[25-21]] A, R[IR[20-16]] B, S S

30. R – Arithmetic – Logic Instruction
op rd, rs, rt
R[rs] op R[rt] R [rd]
Op = R-type
S0 M[PC] IR, PC PC, S S
S1 R[IR[25-21]] A, R[IR[20-16]] B, S S
S6 A op B ALUOut, S S

31. R – Arithmetic – Logic Instruction
op rd, rs, rt
R[rs] op R[rt] R [rd]
Op = R-type
S0 M[PC] IR, PC PC, S S
S1 R[IR[25-21]] A, R[IR[20-16]] B, S S
S6 A op B ALUOut, S S
S7 ALUOut R[IR[15-11]], S S

32. IR timing requires a write control signalD a t a P C A d d r e s s IR A R e g i s t e r # I n s t r u c t i o n M e m o r y R e g i s t e r s A L U A L U O u t o r d a t a M e m o r y R e g i s t e r # d a t a B D a t a r e g i s t e r R e g i s t e r #
MDR
IR timing requires a write control signal

33. beq rs, rt, imm I -type
op rs rt address/ immediate
Zero =1 iff $rs - $rt = 0
Zero (PC+4) + Zero SUM[ (ShLt2[Sign_Ext(imm16)])+PC+4] PC

34. beq rs, rt, imm I -type
Zero (PC+4) + Zero SUM[ (ShLt2[Sign_Ext(imm16)])+PC+4] PC
Op = ‘BEQ’
S0 M[PC] IR, PC PC, S S

35. beq rs, rt, imm I -type
Zero (PC+4) + Zero SUM[ (ShLt2[Sign_Ext(imm16)])+PC+4] PC
Op = ‘BEQ’
S0 M[PC] IR, PC PC, S S
S1 R[IR[25-21]] A, R[IR[20-16]] B,
PC + shlt2[sign_ext(IR[15-0])] ALUOut, S S
The transfers for S1 are the same for all instructions
except the next control state which depends on the
op code

36. beq rs, rt, imm I -type
Zero (PC+4) + Zero SUM[ (ShLt2[Sign_Ext(imm16)])+PC+4] PC
Op = ‘BEQ’
S0 M[PC] IR, PC PC, S S
S1 R[IR[25-21]] A, R[IR[20-16]] B,
PC + shlt2[sign_ext(IR[15-0])] ALUOut, S S
S8 Zero PC + Zero ALUOut PC, S S

37. IR timing requires a write control signalD a t a P C A d d r e s s IR A R e g i s t e r # I n s t r u c t i o n M e m o r y R e g i s t e r s A L U A L U O u t o r d a t a M e m o r y R e g i s t e r # d a t a B D a t a r e g i s t e r R e g i s t e r #
MDR
IR timing requires a write control signal

38. Jump Instruction j Label go to Label op address 2 address
6 bits bits
The complete 32 bit address is :
address 00
4 bits bits bits
Upper 4 bits of the Program Counter, PC
jump uses word addresses
address * 4 = address:00
This is Pseudodirect Addressing.
Note: 256 MB word boundaries

39. j Label go to Label Op = ‘J’ S0 M[PC] IR, PC + 4 PC, S1 S op address 2
6 bits bits
Op = ‘J’
S0 M[PC] IR, PC PC, S S

40. PC + shlt2[sign_ext(IR[15-0])] ALUOut, S9 S
j Label go to Label
op address 2
address
6 bits bits
Op = ‘J’
S0 M[PC] IR, PC PC, S S
S1 R[IR[25-21]] A, R[IR[20-16]] B,
PC + shlt2[sign_ext(IR[15-0])] ALUOut, S S

41. PC + shlt2[sign_ext(IR[15-0])] ALUOut, S9 S
j Label go to Label
op address 2
address
6 bits bits
Op = ‘J’
S0 M[PC] IR, PC PC, S S
S1 R[IR[25-21]] A, R[IR[20-16]] B,
PC + shlt2[sign_ext(IR[15-0])] ALUOut, S S
S PC[31-28] : shlt2(IR[25-0]) PC, S S

42. IR timing requires a write control signalD a t a P C A d d r e s s IR A R e g i s t e r # I n s t r u c t i o n M e m o r y R e g i s t e r s A L U A L U O u t o r d a t a M e m o r y R e g i s t e r # d a t a B D a t a r e g i s t e r R e g i s t e r #
MDR
IR timing requires a write control signal

43. State Register Transfers
S0 M[PC] IR, PC PC, S S

44. State Register Transfers
S0 M[PC] IR, PC PC, S S
S1 R[IR[25-21]] A, R[IR[20-16]] B,
PC + shlt2[sign_ext(IR[15-0])] ALUOut,
(‘LW’+’SW’)S2 + ‘R’S6 + ‘BEQ’S8 + ‘J’S S

45. Load Word & Store Word ( I – type )
lw rt, imm16 (rs) or sw rt, imm16 ( rs)
op rs rt address/ immediate
31, , 25, , 20, , 15,
lw # load word
M[ R[rs] + sign_ext(imm16) ] R[rt]
sw # store word
R[rt] M[ R[rs] + sign_ext(imm16) ]

46. State Register Transfers
S0 M[PC] IR, PC PC, S S
S1 R[IR[25-21]] A, R[IR[20-16]] B,
PC + shlt2[sign_ext(IR[15-0])] ALUOut,
(‘LW’+’SW’)S2 + ‘R’S6 + ‘BEQ’S8 + ‘J’S S
S2 A + sign_ext(IR[15-0]) ALUOut,
‘LW’S3 + ‘SW’S5 S

47. State Register Transfers
S0 M[PC] IR, PC PC, S S
S1 R[IR[25-21]] A, R[IR[20-16]] B,
PC + shlt2[sign_ext(IR[15-0])] ALUOut,
(‘LW’+’SW’)S2 + ‘R’S6 + ‘BEQ’S8 + ‘J’S S
S2 A + sign_ext(IR[15-0]) ALUOut,
‘LW’S3 + ‘SW’S5 S
S3 M[ ALUOut] MDR, S4 S

48. State Register Transfers
S0 M[PC] IR, PC PC, S S
S1 R[IR[25-21]] A, R[IR[20-16]] B,
PC + shlt2[sign_ext(IR[15-0])] ALUOut,
(‘LW’+’SW’)S2 + ‘R’S6 + ‘BEQ’S8 + ‘J’S S
S2 A + sign_ext(IR[15-0]) ALUOut,
‘LW’S3 + ‘SW’S5 S
S3 M[ ALUOut] MDR, S4 S
S MDR R[ IR[20-16]], S0 S

49. State Register Transfers
S0 M[PC] IR, PC PC, S S
S1 R[IR[25-21]] A, R[IR[20-16]] B,
PC + shlt2[sign_ext(IR[15-0])] ALUOut,
(‘LW’+’SW’)S2 + ‘R’S6 + ‘BEQ’S8 + ‘J’S S
S2 A + sign_ext(IR[15-0]) ALUOut,
‘LW’S3 + ‘SW’S5 S
S3 M[ ALUOut] MDR, S4 S
S MDR R[ IR[20-16]], S0 S
S5 B M[ ALUOut], S0 S

50. R – Arithmetic – Logic Instruction
op rd, rs, rt
R[rs] op R[rt] R [rd]
op rs rt rd shamt funct

51. State Register Transfers
S0 M[PC] IR, PC PC, S S
S1 R[IR[25-21]] A, R[IR[20-16]] B,
PC + shlt2[sign_ext(IR[15-0])] ALUOut,
(‘LW’+’SW’)S2 + ‘R’S6 + ‘BEQ’S8 + ‘J’S S
S2 A + sign_ext(IR[15-0]) ALUOut,
‘LW’S3 + ‘SW’S5 S
S3 M[ ALUOut] MDR, S4 S
S MDR R[ IR[20-16]], S0 S
S5 B M[ ALUOut], S0 S
S6 A op B ALUOut, S7 S

52. State Register Transfers
S0 M[PC] IR, PC PC, S S
S1 R[IR[25-21]] A, R[IR[20-16]] B,
PC + shlt2[sign_ext(IR[15-0])] ALUOut,
(‘LW’+’SW’)S2 + ‘R’S6 + ‘BEQ’S8 + ‘J’S S
S2 A + sign_ext(IR[15-0]) ALUOut,
‘LW’S3 + ‘SW’S5 S
S3 M[ ALUOut] MDR, S4 S
S MDR R[ IR[20-16]], S0 S
S5 B M[ ALUOut], S0 S
S6 A op B ALUOut, S7 S
S7 ALUOut R[IR[15-11]], S0 S

53. beq rs, rt, imm I -type
op rs rt address/ immediate
Zero =1 iff $rs - $rt = 0
Zero (PC+4) + Zero SUM[ (ShLt2[Sign_Ext(imm16)])+PC+4] PC

54. State Register Transfers
S0 M[PC] IR, PC PC, S S
S1 R[IR[25-21]] A, R[IR[20-16]] B,
PC + shlt2[sign_ext(IR[15-0])] ALUOut,
(‘LW’+’SW’)S2 + ‘R’S6 + ‘BEQ’S8 + ‘J’S S
S2 A + sign_ext(IR[15-0]) ALUOut,
‘LW’S3 + ‘SW’S5 S
S3 M[ ALUOut] MDR, S4 S
S MDR R[ IR[20-16]], S0 S
S5 B M[ ALUOut], S0 S
S6 A op B ALUOut, S7 S
S7 ALUOut R[IR[15-11]], S0 S
S8 Zero PC + Zero ALUOut PC, S0 S

55. Jump Instruction j Label go to Label op address 2 address
6 bits bits
The complete 32 bit address is :
address 00
4 bits bits bits
Upper 4 bits of the Program Counter, PC
jump uses word addresses
address * 4 = address:00
This is Pseudodirect Addressing.
Note: 256 MB word boundaries

56. State Register Transfers
S0 M[PC] IR, PC PC, S S
S1 R[IR[25-21]] A, R[IR[20-16]] B,
PC + shlt2[sign_ext(IR[15-0])] ALUOut,
(‘LW’+’SW’)S2 + ‘R’S6 + ‘BEQ’S8 + ‘J’S S
S2 A + sign_ext(IR[15-0]) ALUOut,
‘LW’S3 + ‘SW’S5 S
S3 M[ ALUOut] MDR, S4 S
S MDR R[ IR[20-16]], S0 S
S5 B M[ ALUOut], S0 S
S6 A op B ALUOut, S7 S
S7 ALUOut R[IR[15-11]], S0 S
S8 Zero PC + Zero ALUOut PC, S0 S
S PC[31-28] : shlt2(IR[25-0]) PC, S0 S

57. What would “Halt” look like?
S0 M[PC] IR, PC PC, S S
S1 R[IR[25-21]] A, R[IR[20-16]] B,
PC + shlt2[sign_ext(IR[15-0])] ALUOut,
(‘LW’+’SW’)S2 + ‘R’S6 + ‘BEQ’S8 + ‘J’S9
+ ‘Halt’ S S
S10

58. What would “Halt” look like?
S0 M[PC] IR, PC PC, S S
S1 R[IR[25-21]] A, R[IR[20-16]] B,
PC + shlt2[sign_ext(IR[15-0])] ALUOut,
(‘LW’+’SW’)S2 + ‘R’S6 + ‘BEQ’S8 + ‘J’S9
+ ‘Halt’ S S
S S10 S

59. What would “Start” look like?
Start S0 S, ‘boot’ PC

60. What if a Memory Read took 3 clock cycles?
Instead of
S0 M[PC] IR, PC PC, S S
It would be
S M[PC] IR S1 S
S S2 S
S PC PC S3 S